HFC-S Cologne Chip AG, HFC-S Datasheet - Page 9

• Manufacturer Part Number: HFC-S
• Description: Isdn S/t HDLC Basic Rate Controller
• Manufacturer: Cologne Chip AG

2.5
2.6
2.7
(e. g. for PCM codecs)
March 1997
Pin No.
Pin No.
74
75
76
77
78
50
79
80
82
83
85
86
87
88
91
92
u)
Oscillator
PCM30 bus interface
internal pull up
PCM30 Timeslot enable signals
SRA10
SRA11
SRA12
SRA13
SRA14
/SRDS
/SRCS
/SRWR
OSC_IN
OSC_OUT
C4IO
F0IO
STIO1
STIO2
F1_A
F1_B
Pin Name
Pin Name
Tristate
Tristate
Output
Output
I/OT
I/OT
Input
Input
I/O
I/O
O
O
O
O
O
O
O
O
O
O
O
I
u)
u)
u)
u)
all
all
all
all
all
all
SRAM address bus bit 10
SRAM address bus bit 11
SRAM address bus bit 12
SRAM address bus bit 13
SRAM address bus bit 14 (MSB)
SRAM control signals
Data strobe to external device
SRAM chip select
SRAM write enable
Oscillator input or quarz connection
12.288 Mhz for HFC-S with PCM30 bus function
Oscillator output or quarz connection
Mode Function
Function
4.096 Mhz clock
PCM30 bus clock master output
PCM30 bus clock slave input (reset default)
Frame synchronisation, 8kHz pulse for PCM30
bus frame synchronisation
PCM30 bus master output
PCM30 bus slave input (reset default)
PCM30 bus databus I
Slotwise programmable as input or output
PCM30 bus databus II
Slotwise programmable as input or output
enable signal for external CODEC A
Programmable as positive (reset default) or
negative pulse.
enable signal for external CODEC B
Programmable as positive (reset default) or
negative pulse.
HFC-S
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