HFC-S Cologne Chip AG, HFC-S Datasheet - Page 15

• Manufacturer Part Number: HFC-S
• Description: Isdn S/t HDLC Basic Rate Controller
• Manufacturer: Cologne Chip AG

3.2.1 DMA access in processor mode
In processor mode a simple DMA access to the auxiliary channels of the PCM30 interface is
possible. This is useful for tone synthetisation or for voice recording. DMAREQ is asserted every
125µs at a BUSY/NOBUSY transition. DMAREQ is reset when /DMAAK is active.
Table 2: DMA access in processor mode
*)
March 1997
Mode
1-pulse latches I/O address.
2,3,4
2
2
2
2
3
3
3
3
4
4
4
4
/DMAAK0
1
0
0
1
1
0
0
1
1
0
0
1
1
/DMAAK1
1
1
1
0
0
1
1
0
0
1
1
0
0
/CS
X
X
X
X
X
X
X
X
X
X
X
X
X
ALE /IOR
0
0
0
0
X
1
1
1
1
0
0
0
0
*)
*)
*)
*)
/DS
X
X
X
X
X
1
0
1
0
1
0
1
0
/IOW
R/W
X
0
1
0
1
0
1
0
1
0
1
0
1
Function
no DMA
DMA read AUX1
DMA write AUX1
DMA read AUX2
DMA write AUX2
DMA read AUX1
DMA write AUX1
DMA read AUX2
DMA write AUX2
DMA read AUX1
DMA write AUX1
DMA read AUX2
DMA write AUX2
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HFC-S