HFC-S Cologne Chip AG, HFC-S Datasheet - Page 7

• Manufacturer Part Number: HFC-S
• Description: Isdn S/t HDLC Basic Rate Controller
• Manufacturer: Cologne Chip AG

March 1997
Pin No.
15
16
17
18
21
22
23
24
25
26
27
28
31
32
14
If DMA acknowledge signals /DMAAK0 and /DMAAK1 are active, the fu nction of the
read/write enables is inverted. This means a read command on the controller databus
writes the AUX-Channel register and a write command reads the register. The address on
the address bus (SA0-SA7) is ignored.
1)
important!
open drain, external pull up resistor required
SA9
/DMAAK1
/AEN
/CS
IOCHRDY
/IOR
/DS
/IOW
R/W
BD0
BD1
BD2
BD3
BD4
BD5
BD6
BD7
BUSDIR
ALE
Pin Name
Tristate
Output
Input
OT
OT
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
I
I
I
I
I
I
I
I
I
1)
1)
1
2,3,4
1
2,3,4
1
2,3,4
1,3,4
2
1,3,4
2
all
all
all
all
all
all
all
all
all
Mode Function
address bit 9
DMA acknowledge channel 1
direct access on PCM30 bus AUX2 channel
dataregister (low active)
PC bus address enable
chipselect low active
I/O channel ready
low active wait signal for external processor
I/O read enable
I/O data strobe
I/O write enable
Read/Write select (WR='0')
Databus bit 0 (LSB)
Databus bit 1
Databus bit 2
Databus bit 3
Databus bit 4
Databus bit 5
Databus bit 6
Databus bit 7 (MSB)
Databus direction signal for external busdriver
'0'
Address latch enable
ALE to GND and IIOSEL0-3 0000: mode 1
ALE to VDD and IIOSEL0-3=0000:
ALE to GND and IIOSEL0-3=0000:
pulse on ALE and IIOSEL0-3=0000: mode 4
BD0-BD7 are outputs
mode 2
mode 3
HFC-S
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