HFC-S Cologne Chip AG, HFC-S Datasheet - Page 29

• Manufacturer Part Number: HFC-S
• Description: Isdn S/t HDLC Basic Rate Controller
• Manufacturer: Cologne Chip AG

March 1997
Name
SCTRL
TEST
(31h)
(32h)
Bits
0
1
2
3
4
5
6
7
0
7..1
r/w
w
w
w
w
w
w
w
w
w
w
Function
B-channel enable
'0'
'1'
'0'
'1'
S/T-interface mode
'0'
'1'
D-channel priority
'0'
'1'
S/Q bit transmission
'0'
'1'
'0'
'1'
TX_LO line setup
'0'
'1'
Power down
'0'
'1'
Power down mode bit
'0'
'1'
must be set to '0'
B1 send data disabled (permanent 1 sent in activated
states, reset default)
B1 data enabled
B2 send data disabled (permanent 1 sent in activated
states, reset default)
B2 data enabled
TE mode (reset default)
NT mode
high priority 8/9 (reset default)
low priority 10/11
S/Q bit disable (reset default)
S/Q bit enable
normal operation (reset default)
send 96kHz transmit test signal (alternating zeros)
only in states 4, 6, 7 (TE) and 2, 3 (NT)
capacitive line mode for normal S/T-interface
(reset default)
non capacitive line mode
power up, oscillator active (reset default)
power down, oscillator stopped
S/T awake disable (reset default)
Power up can only be programmed by register
access (SCTRL bit 7).
S/T awake enable. Oscillator starts on every non
INFO0 S/T signal.
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HFC-S