HFC-S Cologne Chip AG, HFC-S Datasheet - Page 20

• Manufacturer Part Number: HFC-S
• Description: Isdn S/t HDLC Basic Rate Controller
• Manufacturer: Cologne Chip AG

3.5
There are 6 FIFOs with 6 HDLC-Controllers in the HFC-S. The HDLC circuits are located on the
S/T device side of the HFC-S. So always plain data is stored in the FIFO. Zero insertion and deletion
is done:
– if the data goes to the S/T device in send FIFOs and
– when the HDLC data comes from the S/T device or PCM30 bus in receive operation.
There are a send and a receive FIFO for each of the two B-channels and for the D-channel.
The FIFOs are realized as ring buffers in the external SRAM. To control them there are some
counters.
Z1: FIFO input counter
Z2: FIFO output counter
Each counter points to a byte position in the SRAM. On a FIFO input operation Z1 is incremented.
On an output operation Z2 is incremented.
After every pulse on the F0IO signal the HFC-S goes into busy cycle and two HDLC-bytes are
written into the S/T interface (FIFOs No. 0 and 2) and two HDLC-bytes are read from the S/T
interface (FIFOs No. 1 and 3).
D-channel data is handled in a similar way.
If Z1 = Z2 the FIFO is empty.
Additionally there are two counters F1 and F2 for every FIFO channel (5Bit for B-channel, 4Bit for
D-channel). They count the HDLC-frames in the FIFOs and form a ring buffer as Z1 and Z2 do, too.
Again F1 is incremented when a complete frame has been received and stored in the FIFO. F2 is
incremented when a complete frame has been read from the FIFO.
If F1 = F2 there is no complete frame in the FIFO.
When the RESET line is active or software reset is active Z1, Z2, F1 and F2 are all initialized to all
1s.
March 1997
Instead of the S/T interface also PCM30 bus is selectable for each B-channel (see CONNECT
register).
The counter state 0200h of the Z-counters follows counter state 1FFFh in the B-channel FIFOs.
If 8k RAM mode is selected counter state 1A00h of the Z-counters follows counter state 1FFFh
in the B-channel FIFOs.
The counter state 000h of the Z-counters follows counter state 1FFh in the D-channel FIFOs.
The counter state 00h of the F-counters follows counter state 1Fh in the B-channel FIFOs.
The counter state 10h of the F-counters follows counter state 1Fh in the D-channel FIFOs.
important!
important!
FIFOs
B-channel D-channel
13 Bit
13 Bit
9 Bit
9 Bit
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HFC-S