GS1560A Gennum Corporation, GS1560A Datasheet - Page 48

• Manufacturer Part Number: GS1560A
• Description: Reclocking Deserializer For HD-SDI, Sd-sdi & Dvb-asi With Loop Thru Cable Driver. 3.3/1.8V Supply.
• Manufacturer: Gennum Corporation

3.11 PARALLEL DATA OUTPUTS
3.11 PARALLEL DATA OUTPUTS
3.11 PARALLEL DATA OUTPUTS
3.11 PARALLEL DATA OUTPUTS
Data outputs leave the device on the rising edge of PCLK
as shown in Figures 12a and 12b.
The data may be scrambled or unscrambled, framed or
unframed, and may be presented in 10-bit or 20-bit format.
The output data bus width is controlled independently from
the internal data bus width by the 20bit/10bit input pin.
Likewise, the output data format is defined by the setting of
the external SD/HD, SMPTE_BYPASS and DVB_ASI pins.
Recall that in slave mode, these pins are set by the
application layer as inputs to the device. In master mode,
however, the GS1560A sets these pins as output status
signals.
3.11.1 Parallel Data Bus Buffers
The parallel data outputs of the GS1560A are driven by
high-impedance buffers which support both LVTTL and
LVCMOS levels. These buffers use a separate power supply
of +3.3V DC supplied via the IO_VDD and IO_GND pins.
All output buffers, including the PCLK output, may be driven
to a high-impedance state if the RESET_TRST signal is
asserted LOW, or if power on reset is active.
Note that the timing characteristics of the parallel data
output buffers are optimized for 10-bit HD operation. As
shown in figure 12a, the output data hold time for HD is
1.5ns.
Due to this optimization, however, the output data hold time
for SD data is so small that the rising edge of the PCLK is
nearly incident with the data transition. To improve output
hold time at SD rates, the PCLK output is inverted is SD
mode, (SD/HD = HIGH). This is shown in figure 12b.
GENNUM CORPORATION
Control signal
DOUT[19:0]
output
PCLK
Fig. 12a HD PCLK to Data Timing
HD MODE
DATA
t
OH
t
OD
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3.11.2 Parallel Output in SMPTE Mode
When the device is operating in SMPTE mode, (see section
3.7), both SD and HD data may be presented to the output
bus in either multiplexed or demultiplexed form depending
on the setting of the 20bit/10bit input pin.
In 20-bit mode, (20bit/10bit = HIGH), the output data will be
word aligned, demultiplexed luma and chroma data. Luma
words will always appear on DOUT[19:10] while chroma
words will occupy DOUT[9:0].
In 10-bit mode, (20bit/10bit = LOW), the output data will be
word aligned, multiplexed luma and chroma data. The data
will be presented on DOUT[19:10], and the device will force
DOUT[9:0] LOW.
3.11.3 Parallel Output in DVB-ASI Mode
When operating in DVB-ASI mode, (see section 3.8), the
GS1560A automatically configures the output port for 10-bit
operation regardless of the setting of the 20bit/10bit pin.
The extracted 8-bit data words will be presented on
DOUT[17:10] such that DOUT17 = HOUT is the most
significant bit of the decoded transport stream data and
DOUT10 = AOUT is the least significant bit.
In addition, DOUT19 and DOUT18 will be configured as the
DVB-ASI
respectively. See section 3.8.2 for a description of these
DVB-ASI specific output signals.
DOUT[9:0] will be forced LOW when the GS1560A is
operating in DVB-ASI mode.
3.11.4 Parallel Output in Data-Through Mode
When operating in Data-Through mode, (see section 3.9),
the GS1560A presents data to the output data bus without
performing any decoding, descrambling or word-alignment.
As described in section 3.9, the data bus outputs will be
forced to logic LOW if the device is set to operate in master
mode but cannot identify SMPTE TRS ID or DVB-ASI sync
words in the input data stream.
Control signal
DOUT[19:0]
output
PCLK
status
Fig. 12b SD PCLK to Data Timing
signals
SYNCOUT
SD MODE
DATA
t
OH
t
OD
and
WORDERR
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