GS1560A Gennum Corporation, GS1560A Datasheet - Page 29

• Manufacturer Part Number: GS1560A
• Description: Reclocking Deserializer For HD-SDI, Sd-sdi & Dvb-asi With Loop Thru Cable Driver. 3.3/1.8V Supply.
• Manufacturer: Gennum Corporation

3.7 SMPTE FUNCTIONALITY
3.7 SMPTE FUNCTIONALITY
3.7 SMPTE FUNCTIONALITY
3.7 SMPTE FUNCTIONALITY
The GS1560A is said to be in SMPTE mode once the device
has detected SMPTE TRS sync words and locked to the
input data stream as described in section 3.6.1. The device
will remain in SMPTE mode until such time that SMPTE TRS
sync words fail to be detected.
The lock detect block may also drop out of SMPTE mode
under the following conditions:
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TRS word detection is a continuous process and both 8-bit
and 10-bit TRS words will be identified by the device in both
SD and HD modes.
In master mode, the GS1560A sets the SMPTE_BYPASS pin
HIGH and the DVB_ASI pin LOW to indicate that it has
locked to a SMPTE input data stream. When operating in
slave mode, the application layer must assert the DVB_ASI
pin LOW and the SMPTE_BYPASS pin HIGH in order to
enable SMPTE operation.
3.7.1 SMPTE Descrambling and Word Alignment
After serial-to-parallel conversion, the internal 10-bit or 20-
bit data bus is fed to the SMPTE descramble and word
alignment block. The function of this block is to carry out
NRZI-to-NRZ decoding, descrambling according to SMPTE
259M or 292M, and word alignment of the data to the TRS
sync words.
Word alignment occurs when three consecutive valid TRS
words (SAV and EAV inclusive) with the same bit alignment
have been detected (1½ video lines).
In normal operation, re-synchronization of the word
alignment process will only take place when two
consecutive identical TRS word positions have been
detected. When automatic or manual switch line lock
handling is 'actioned', (see section 3.7.3), word alignment
re-synchronization will occur on the next received TRS code
word.
3.7.2 Internal Flywheel
The GS1560A has an internal flywheel which is used in the
generation of internal / external timing signals, in the
detection and correction of certain error conditions and in
automatic video standards detection. It is only operational
in SMPTE mode.
The flywheel consists of a number of counters and
comparators operating at video pixel and video line rates.
These counters maintain information about the total line
length, active line length, total number of lines per field /
GENNUM CORPORATION
RESET_TRST is asserted LOW
CDx is HIGH
SMPTE_BYPASS is asserted LOW in slave mode
DVB_ASI is asserted HIGH in slave mode
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frame, and total active lines per field / frame for the
received video stream.
The flywheel 'learns' the video standard by timing the
horizontal and vertical reference information contained in
the TRS ID words of the received video stream. Full
synchronization of the flywheel to the received video
standard therefore requires one complete video frame.
Once synchronization has been achieved, the flywheel will
continue to monitor the received TRS timing information to
maintain synchronization.
The FW_EN/DIS input pin controls the synchronization
mechanism of the flywheel. When this input signal is LOW,
the flywheel will re-synchronize all pixel and line based
counters on every received TRS ID word.
When FW_EN/DIS is held HIGH, re-synchronization of the
pixel and line based counters will only take place when a
consistent synchronization error has been detected. Two
consecutive video lines with identical TRS timing different to
the current flywheel timing must occur to initiate re-
synchronization of the counters. This provides a measure of
noise immunity to internal and external timing signal
generation.
The flywheel will be disabled should the LOCKED signal or
the RESET_TRST signal be LOW.
transistion on either signal will cause the flywheel to re-
acquire synchronization on the next received TRS word,
regardless of the setting of the FW_EN/DIS pin.
3.7.3 Switch Line Lock Handling
The principal of switch line lock handling is that the
switching of synchronous video sources will only disturb the
horizontal timing and alignment of the stream, whereas the
vertical timing remains in synchronization.
To account for the horizontal disturbance caused by a
synchronous switch, it is necessary to re-synchronize the
flywheel immediately after the switch has taken place.
Rapid re-synchronization of the GS1560A to the new video
standard can be achieved by controlling the flywheel using
the FW_EN/DIS pin.
At every PCLK cycle the device samples the FW_EN/DIS
pin. When a logic LOW to HIGH transition at this pin is
detected anywhere within the active line, the flywheel will
re-synchronize immediately to the next TRS word. This is
shown in Figures 7a,b.
To ensure switch line lock handling, the FW_EN/DIS signal
should be LOW for a minimum of one PCLK cycle
(maximum one video line) anywhere within the active
portion of the line on which the switch has taken place.
A LOW to HIGH
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