GS1560A Gennum Corporation, GS1560A Datasheet - Page 27

• Manufacturer Part Number: GS1560A
• Description: Reclocking Deserializer For HD-SDI, Sd-sdi & Dvb-asi With Loop Thru Cable Driver. 3.3/1.8V Supply.
• Manufacturer: Gennum Corporation

Table 1: Serial Digital Loop-Through Output Status
3.5 SERIAL-TO-PARALLEL CONVERSION
3.5 SERIAL-TO-PARALLEL CONVERSION
3.5 SERIAL-TO-PARALLEL CONVERSION
3.5 SERIAL-TO-PARALLEL CONVERSION
The retimed data and phase-locked clock signals from the
reclocker are fed to the serial-to-parallel converter. The
function of this block is to extract 10-bit or 20-bit parallel
data words from the reclocked serial data stream and
present them to the SMPTE and DVB-ASI word alignment
blocks simultaneously.
3.6 MODES OF OPERATION
3.6 MODES OF OPERATION
3.6 MODES OF OPERATION
3.6 MODES OF OPERATION
The GS1560A has two basic modes of operation which
determine how the lock detect block controls the integrated
reclocker. Master mode is enabled when the application
layer sets the MASTER/SLAVE pin HIGH, and slave mode is
enabled when MASTER/SLAVE is set LOW.
3.6.1 Lock Detect
The lock detect block controls the center frequency of the
integrated reclocker to ensure lock to the received serial
digital data stream is achieved, and indicates via the
LOCKED output pin that the device has detected the
appropriate sync words.
Lock detection is a continuous process, which begins at
device power up or after a system reset, and continues until
the device is powered down or held in reset.
The lock detection algorithm first determines if a valid serial
digital input signal has been presented to the device by
sampling the internal carrier_detect signal. As described in
section 3.2.2, this signal will be LOW when a good serial
digital input signal has been detected.
If the carrier_detect signal is HIGH, the serial data into the
device is considered invalid, and the VCO frequency will be
set to the center of the pull range. The LOCKED pin will be
LOW and all outputs of the device except for the PCLK
output will be muted. Instead, the PCLK output frequency
will operate within +/-3% of the rates shown in Table 16 of
section 3.11.5.
GENNUM CORPORATION
RECLOCKED
BUFFERED
MUTED
MUTED
RECLOCKED
BUFFERED
MUTED
*NOTE: LOCKED = HIGH if and only if CD = LOW
SDO
SDO
HIGH
HIGH
LOW
LOW
LOW
LOW
LOW
CD
CD
MASTER MODE
SLAVE MODE
LOCKED
LOCKED
LOW*
LOW*
HIGH
HIGH
LOW
LOW
X
(OUTPUT)
RC_BYP
RC_BYP
(INPUT)
HIGH
HIGH
HIGH
LOW
LOW
LOW
X
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NOTE: When the device is operating in DVB-ASI Slave
mode only, the parallel outputs will not mute when the
carrier_detect signal is HIGH. The LOCKED signal will
function normally.
If a valid input signal has been detected, and the device is
in master mode, the lock algorithm will enter a hunt phase
where four attempts are made to detect the presence of
either SMPTE TRS sync words or DVB-ASI sync words. At
each attempt, the center frequency of the reclocker will be
toggled between 270Mb/s and 1.485Gb/s.
Assuming that a valid SMPTE or DVB-ASI signal has been
applied to the device, aynchronous lock times will be as
listed in the AC Characteristics Table, (section 2.3).
In slave mode, the application layer fixes the center
frequency of the reclocker such that the lock algorithm will
attempt to lock within the single data rate determined by the
setting of the SD/HD pin. Asynchronous lock times are also
listed in the AC Characteristics Table, (section 2.3).
NOTE: The PCLK output will continue to operate during the
lock detection process. The frequency may toggle between
148MHz and 27MHz when the 20bit/10bit pin is set LOW,
or between 74MHz and 13.5MHz when 20bit/10bit is set
HIGH.
For SMPTE and DVB-ASI inputs, the lock detect block will
only assert the LOCKED output signal HIGH if (1) the
reclocker has locked to the input data stream as indicated
by the internal pll_lock signal, AND (2) TRS or DVB-ASI
sync words have been correctly identified.
If after four attempts lock has not been achieved, the lock
detection algorithm will enter into PLL lock mode. In this
mode, the reclocker will attempt to lock to the input data
stream without detecting SMPTE TRS or DVB-ASI sync
words. This unassisted process can take up to 10ms to
achieve lock.
When reclocker lock as indicated by the internal pll_lock
signal is achieved in this mode, one of the following will
occur:
1. In slave mode, data will be passed directly to the
2. In master mode, the LOCKED signal will be asserted
parallel outputs without any further processing taking
place and the LOCKED signal will be asserted HIGH if
and only if the SMPTE_BYPASS and DVB_ASI input pins
are set LOW; or
LOW, the parallel outputs will be latched to logic LOW,
and the SMPTE_BYPASS and DVB_ASI output signals
will also be set LOW.
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