GS1560A Gennum Corporation, GS1560A Datasheet - Page 14

• Manufacturer Part Number: GS1560A
• Description: Reclocking Deserializer For HD-SDI, Sd-sdi & Dvb-asi With Loop Thru Cable Driver. 3.3/1.8V Supply.
• Manufacturer: Gennum Corporation

1.2 PIN DESCRIPTIONS (CONTINUED)
GENNUM CORPORATION
NUMBER
PIN DESCRIPTIONS (CONTINUED)
PIN DESCRIPTIONS (CONTINUED)
PIN DESCRIPTIONS (CONTINUED)
PIN
65
66
67
69
FW_EN/DIS
NAME
CANC
YANC
PCLK
Synchronous
Synchronous
Synchronous
with PCLK
with PCLK
TIMING
Non
-
Output
Output
Output
TYPE
Input
14 of 55
STATUS SIGNAL OUTPUT
Signal levels are LVCMOS/LVTTL compatible.
Used to indicate the presence of ancillary data in the video stream.
HD Mode (SD/HD = LOW)
The YANC signal will be HIGH when the device has detected VANC or
HANC data in the luma video stream and LOW otherwise.
SD Mode (SD/HD = LOW)
For 20-bit demultiplexed data (20bit/10bit = HIGH), the YANC signal will
be HIGH when VANC or HANC data is detected in the luma video stream
and LOW otherwise.
For 10-bit multiplexed data (20bit/10bit = LOW), the YANC signal will be
HIGH when VANC or HANC data is detected anywhere in the data stream
and LOW otherwise.
STATUS SIGNAL OUTPUT
Signal levels are LVCMOS/LVTTL compatible.
Used to indicate the presence of ancillary data in the video stream.
HD Mode (SD/HD = LOW)
The CANC signal will be HIGH when the device has detected VANC or
HANC data in the chroma video stream and LOW otherwise.
SD Mode (SD/HD = LOW)
For 20-bit demultiplexed data (20bit/10bit = HIGH), the CANC signal will
be HIGH when VANC or HANC data is detected in the chroma video
stream and LOW otherwise.
For 10-bit multiplexed data (20bit/10bit = LOW), the CANC signal will be
HIGH when VANC or HANC data is detected anywhere in the data stream
and LOW otherwise.
CONTROL SIGNAL INPUT
Signal levels are LVCMOS/LVTTL compatible.
Used to enable or disable the noise immune flywheel of the device.
When set HIGH, the internal flywheel is enabled. This flywheel is used in
the extraction and generation of TRS timing signals, in automatic video
standards detection, and in manual switch line lock handling.
When set LOW, the internal flywheel is disabled and TRS correction and
insertion is unavailable.
PARALLEL DATA BUS CLOCK
Signal levels are LVCMOS/LVTTL compatible.
HD 20-bit mode
HD 10-bit mode
SD 20-bit mode
SD 10-bit mode
DESCRIPTION
PCLK = 74.25MHz or 74.25/1.001MHz
PCLK = 148.5MHz or 148.5/1.001MHz
PCLK = 13.5MHz
PCLK = 27MHz
27360-1