GS1560A Gennum Corporation, GS1560A Datasheet - Page 25

• Manufacturer Part Number: GS1560A
• Description: Reclocking Deserializer For HD-SDI, Sd-sdi & Dvb-asi With Loop Thru Cable Driver. 3.3/1.8V Supply.
• Manufacturer: Gennum Corporation

3. DETAILED DESCRIPTION
3. DETAILED DESCRIPTION
3. DETAILED DESCRIPTION
3. DETAILED DESCRIPTION
3.1 FUNCTIONAL OVERVIEW
3.1 FUNCTIONAL OVERVIEW
3.1 FUNCTIONAL OVERVIEW
3.1 FUNCTIONAL OVERVIEW
The GS1560A is a multi-rate reclocking deserializer with an
integrated serial digital loop-through output. When used in
conjunction with the multi-rate GS1524 Adaptive Cable
Equalizer and the external GO1525 Voltage Controlled
Oscillator, a receive solution for input data at 1.485Gb/s,
1.485/1.001Gb/s or 270Mb/s is realized.
The device has two basic modes of operation which
determine preceisely how SMPTE or DVB-ASI compliant
input data streams are reclocked and processed.
In master mode, (MASTER/SLAVE = HIGH), the GS1560A
will automatically detect, reclock, deserialize and process
SD SMPTE 259M-C, HD SMPTE 292M, or DVB-ASI input
data.
In slave mode, (MASTER/SLAVE = LOW), the application
layer must set external device pins for the correct reception
of either SMPTE or DVB-ASI data. Slave mode also
supports the reclocking and deserializing of data not
conforming to SMPTE or DVB-ASI streams.
The provided serial loop-through outputs may be selected
as either buffered or reclocked versions of the input signal
and feature a high impedance mode, output mute on loss of
signal and adjustable signal swing.
In the digital signal processing core, several data
processing functions are implemented including error
detection and correction and automatic video standards
detection. These features are all enabled by default, but
may
accessible through the GSPI host interface.
Finally, the GS1560A contains a JTAG interface for
boundary scan test implementations and an active power-
on reset.
3.2 SERIAL DIGITAL INPUT
3.2 SERIAL DIGITAL INPUT
3.2 SERIAL DIGITAL INPUT
3.2 SERIAL DIGITAL INPUT
The GS1560A contains two current mode differential serial
digital input buffers, allowing the device to be connected to
two SMPTE 259M-C or 292M compliant input signals.
Both input buffers have internal 50Ω termination resistors
which are connected to ground via the TERM1 and TERM2
pins. The input common mode level is set by internal
biasing resistors such that the serial digital input signals
must be AC coupled into the device. Gennum recommends
using a capacitor value of 4.7uF to accommodate
pathological signals.
The input buffers use a separate power supply of +1.8V DC
supplied via the BUFF_VDD and PDBUFF_GND pins.
3.2.1 Input Signal Selection
A 2x1 input multiplexer is provided to allow the application
layer to select between the two serial digital input streams
GENNUM CORPORATION
be
individually
disabled
via
internal
registers
25 of 55
using a single external pin. When IP_SEL is set HIGH, serial
digital input 1 (DDI1 / DDI1) is selected as the input to the
GS1560A's reclocker stage. When IP_SEL is set LOW, serial
digital input 2 (DDI2 / DDI2) is selected.
3.2.2 Carrier Detect Input
For each of the differential inputs, an associated carrier
detect input signal is included, (CD1 and CD2). These
signals are generated by Gennum's family of automatic
cable equalizers.
When LOW, CDx indicates that a valid serial digital data
stream is being delivered to the GS1560A by the equalizer.
When HIGH, the serial digital input to the device should be
considered invalid. If no equalizer preceeds the device, the
application layer should set CD1 and CD2 accordingly.
NOTE: If the GS1524 Automatic Cable Equalizer is used,
the MUTE/CD output signal from that device must be
translated to TTL levels before passing to the GS1560A
CDx inputs. See section 4.1 for a recommended transistor
network that will set the correct voltage levels.
A 2x1 input multiplexer is also provided for these signals.
The internal carrier_detect signal is determined by the
setting of the IP_SEL pin and is used by the lock detect
block of the GS1560A to determine the lock status of the
device, (see section 3.6.1).
3.2.3 Single Input Configuration
If the application requires a single differential input, the
second set of inputs may be left unconnected. For greater
noise immunity, however, terminate the unused pair to
+3.3V DC. Tie the associated carrier detect pin HIGH, and
leave termination pin unconnected.
3.3 SERIAL DIGITAL RECLOCKER
3.3 SERIAL DIGITAL RECLOCKER
3.3 SERIAL DIGITAL RECLOCKER
3.3 SERIAL DIGITAL RECLOCKER
The output of the 2x1 serial digital input multiplexer passes
to the GS1560A's internal reclocker stage. The function of
this block is to lock to the input data stream, extract a clean
clock, and retime the serial digital data to remove high
frequency jitter.
The reclocker was designed with a 'hexabang' phase and
frequency detector. That is, the PFD used can identify six
'degrees' of phase / frequency misalignment between the
input data stream and the clock signal provided by the
VCO, and correspondingly signal the charge pump to
produce six different control voltages. This results in fast
and accurate locking of the PLL to the data stream.
In master mode, the operating center frequency of the
reclocker is toggled between 270Mb/s and 1.485Gb/s by
the lock detect block, (see section 3.6.1). In slave mode,
however, the center frequency is determined entirely by the
SD/HD input control signal set by the application layer.
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