MSC8144 Freescale Semiconductor, MSC8144 Datasheet - Page 65

• Manufacturer Part Number: MSC8144
• Description: Quad Core Digital Signal Processor
• Manufacturer: Freescale Semiconductor

3
The following sections discuss areas to consider when the MSC8144 device is designed into a system.
3.1
3.1.1
Use the following guidelines for power-on sequencing:
External voltage applied to any input line must not exceed the related to this port I/O supply by more than 0.6 V at any time,
including during power-up. Some designs require pull-up voltages applied to selected input lines during power-up for
configuration purposes. This is an acceptable exception to the rule during start-up. However, each such input can draw up to 80
mA per input pin per MSC8144 device in the system during start-up. An assertion of the inputs to the high voltage level before
power-up should be with slew rate less than 4V/ns.
The following supplies should rise before any other supplies in any sequence
After the above supplies rise to 90% of their nominal value the following I/O supplies may rise in any sequence (see Figure 45):
Note:
Freescale Semiconductor
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There are no dependencies in power-on/power-off sequence between V
There are no dependencies in power-on/power-off sequence between RapidIO supplies: V
V
V
V
V
V
V
V
V
V
V
1.
2.
3.
4.
5.
6.
DDDDR
DDRIOPLL
DDPLL
DD
DDM3
DDGE1
DDGE2
DDIO
DDM3IO
25M3
Hardware Design Considerations
Start-up Sequencing Recommendations
This recommended power sequencing is different from the MSC8122/MSC8126.
If no pins that require V
If no pins that require V
If the DDR interface is not used, V
If the M3 memory is not used, V
If the RapidIO interface is not used, V
and V
Power-on Sequence
should be coupled with the V
and MV
DDPLL
and other MSC8144 supplies.
REF
coupled together
90%
MSC8144 Quad Core Digital Signal Processor Data Sheet, Rev. 1
Figure 45. V
coupled one to another. MV
DDGE1
DDGE2
DDM3
as a reference supply are used (see Table 1), V
as a reference supply are used (see Table 1), V
DDM3
DD
DDDDR
, V
power rail with extremely low impedance path.
DDSX
, V
DDM3IO
DDM3IO
and MV
, V
REF
DDSXP
and V
, and V
should be either at same time or after V
REF
, and V
25M3
can be tied to GND.
25M3
Power-on Sequence
V
DDRIOPLL
DDM3,
can be tied to GND.
I/O supplies
DDM3
V
DD,
can be tied to GND.
and V
and V
DDPLL
Hardware Design Considerations
DDGE1
DDGE2
DD
supplies.
DDSXC
can be tied to GND.
can be tied to GND.
DDDDR
, V
DDSXP
.
,
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