MSC8144 Freescale Semiconductor, MSC8144 Datasheet - Page 50

• Manufacturer Part Number: MSC8144
• Description: Quad Core Digital Signal Processor
• Manufacturer: Freescale Semiconductor

Electrical Characteristics
2.7.5.9
For the purpose of jitter measurement, the effects of a single-pole high pass filter with a 3 dB point at (baud frequency)/1667 is
applied to the jitter. The data pattern for jitter measurements is the Continuous Jitter Test Pattern (CJPAT) pattern defined in
Annex 48A of IEEE Std. 802.3ae. All lanes of the LP-Serial link shall be active in both the transmit and receive directions, and
opposite ends of the links shall use asynchronous clocks. Four lane implementations shall use CJPAT as defined in Annex 48A.
Single lane implementations shall use the CJPAT sequence specified in Annex 48A for transmission on lane 0. Jitter shall be
measured with AC coupling and at 0 V differential. Jitter measurement for the transmitter (or for calibration of a jitter tolerance
setup) shall be performed with a test procedure resulting in a BER curve such as that described in Annex 48B of IEEE Std.
802.3ae.
2.7.5.10
Transmit jitter is measured at the driver output when terminated into a load of 100 Ω resistive
2.7.5.11
Jitter tolerance is measured at the receiver using a jitter tolerance test signal. This signal is obtained by first producing the sum
of deterministic and random jitter defined in Section 2.7.5.9 and then adjusting the signal amplitude until the data eye contacts
the 6 points of the minimum eye opening of the receive template shown in Figure 15 and Table 37. Note that for this to occur,
the test signal must have vertical waveform symmetry about the average value and have horizontal symmetry (including jitter)
about the mean zero crossing. Eye template measurement requirements are as defined above. Random jitter is calibrated using
a high pass filter with a low frequency corner at 20 MHz and a 20 dB/decade roll-off below this. The required sinusoidal jitter
specified in Section 8.6 is then added to the signal and the test load is replaced by the receiver being tested.
2.7.6
This section describes the general AC timing parameters of the PCI bus. Table 38 provides the PCI AC timing specifications.
50
Output delay
High-Z to Valid Output delay
Valid to High-Z Output delay
Input setup
Input hold
Reset active time after PCI_CLK_IN stable
Reset active to output float delay
Reset active time after power stable
HRESET high to first Configuration Access
Notes:
1.
2.
3.
4.
5.
PCI Timing
See the timing measurement conditions in the PCI 2.2 Local Bus Specifications.
All PCI signals are measured from OV
3.3-V PCI signaling levels.
For purposes of active/float timing measurements, the Hi-Z or off state is defined to be when the total current delivered
through the component pin is less than or equal to the leakage current specification.
Input timings are measured at the pin.
The reset assertion timing requirement for HRESET is in Table 24 and Figure 8
Jitter Test Measurements
Transmit Jitter
Jitter Tolerance
Parameter
MSC8144 Quad Core Digital Signal Processor Data Sheet, Rev. 1
Table 38. PCI AC Timing Specifications
t
t
PCRST-OFF
PCRST-CLK
Symbol
t
DD
t
t
PCRHFA
t
t
t
PCOFF
PCRST
PCVAL
PCON
PCSU
t
PCH
/2 of the rising edge of PCI_SYNC_IN to 0.4 × OV
32M
Min
100
2.0
2.0
7.0
—
—
0
1
33 MHz
Max
11.0
—
28
—
—
—
40
—
—
32M
Min
100
1.0
1.0
3.0
—
—
0
1
±
DD
5% differential to 2.5 GHz.
66 MHz
of the signal in question for
Freescale Semiconductor
Max
6.0
14
40
—
—
—
—
—
—
clocks
Unit
ms
μs
ns
ns
ns
ns
ns
ns