MSC8144 Freescale Semiconductor, MSC8144 Datasheet - Page 2

• Manufacturer Part Number: MSC8144
• Description: Quad Core Digital Signal Processor
• Manufacturer: Freescale Semiconductor

1
2
3
4
5
6
7
List of Figures
Figure 1. MSC8144 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . 3
Figure 2. StarCore SC3400 DSP Core Subsystem Block Diagram 3
Figure 3. MSC8144 FC-PBGA Package, Top View . . . . . . . . . . . . 4
Figure 4. MSC8144 FC-PBGA Package, Bottom View . . . . . . . . . 5
Figure 5. SerDes Reference Clocks Input Stage . . . . . . . . . . . . . 31
Figure 6. Overshoot/Undershoot Voltage for V
Figure 7. Start-Up Sequence with V
Figure 8. Timing for a Reset Configuration Write . . . . . . . . . . . . . 39
Figure 9. Timing for t
Figure 10.DDR SDRAM Output Timing. . . . . . . . . . . . . . . . . . . . . 41
Figure 11.DDR AC Test Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Figure 12.Differential V
2
Pin Assignments and Reset States . . . . . . . . . . . . . . . . . . . . .4
1.1
1.2
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
2.1
2.2
2.3
2.4
2.5
2.6
2.7
Hardware Design Considerations . . . . . . . . . . . . . . . . . . . . . .65
3.1
3.2
3.3
3.4
3.5
Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76
Package Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77
Product Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78
FC-PBGA Ball Layout Diagrams . . . . . . . . . . . . . . . . . . .4
Signal List By Ball Location. . . . . . . . . . . . . . . . . . . . . . .6
Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
Recommended Operating Conditions. . . . . . . . . . . . . .27
Default Output Driver Characteristics . . . . . . . . . . . . . .27
Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . .28
Power Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . .28
DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . .29
AC Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
Start-up Sequencing Recommendations . . . . . . . . . . .65
Power Supply Design Considerations. . . . . . . . . . . . . .66
Connectivity Guidelines . . . . . . . . . . . . . . . . . . . . . . . .66
External DDR SDRAM Selection . . . . . . . . . . . . . . . . .75
Thermal Considerations . . . . . . . . . . . . . . . . . . . . . . . .76
CLKIN Started with V
DDKHMH
PP
of Transmitter or Receiver . . . . . . . . . . 43
. . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
DDIO
MSC8144 Quad Core Digital Signal Processor Data Sheet, Rev. 1
DD
. . . . . . . . . . . . . . . . . . . . . . . 36
Raised Before V
IH
and V
Table of Contents
IL
DDIO
. . . . . . . 35
with
Figure 13.Transmitter Output Compliance Mask . . . . . . . . . . . . . . 46
Figure 14.Single Frequency Sinusoidal Jitter Limits . . . . . . . . . . . 48
Figure 15.Receiver Input Compliance Mask . . . . . . . . . . . . . . . . . 49
Figure 16.PCI AC Test Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Figure 17.PCI Input AC Timing Measurement Conditions . . . . . . . 51
Figure 18.PCI Output AC Timing Measurement Condition . . . . . . 51
Figure 19.TDM Inputs Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Figure 21.TDM Output Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Figure 22.UART Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Figure 23.UART Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Figure 24.Timer Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Figure 25.MII Management Interface Timing . . . . . . . . . . . . . . . . . 55
Figure 26.MII Transmit AC Timing . . . . . . . . . . . . . . . . . . . . . . . . . 55
Figure 27.AC Test Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Figure 28.MII Receive AC Timing . . . . . . . . . . . . . . . . . . . . . . . . . 56
Figure 29.RMII Transmit and Receive AC Timing . . . . . . . . . . . . . 57
Figure 30.AC Test Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Figure 31.SMII Mode Signal Timing. . . . . . . . . . . . . . . . . . . . . . . . 58
Figure 32.RGMII AC Timing and Multiplexing s. . . . . . . . . . . . . . . 59
Figure 33.UTOPIA AC Test Load. . . . . . . . . . . . . . . . . . . . . . . . . . 60
Figure 34.UTOPIA AC Timing (External Clock) . . . . . . . . . . . . . . . 60
Figure 35.UTOPIA AC Timing (Internal Clock) . . . . . . . . . . . . . . . 60
Figure 36.SPI AC Test Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Figure 37.SPI AC Timing in Slave Mode (External Clock). . . . . . . 61
Figure 38.SPI AC Timing in Master Mode (Internal Clock) . . . . . . 62
Figure 39.GPIO Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Figure 40.EE Pin Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Figure 41.Test Clock Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . 63
Figure 42.Boundary Scan (JTAG) Timing . . . . . . . . . . . . . . . . . . . 64
Figure 43.Test Access Port Timing . . . . . . . . . . . . . . . . . . . . . . . . 64
Figure 44.TRST Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Figure 45.V
Figure 47.MSC8144 Mechanical Information, 783-ball FC-PBGA
Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
DDM3
, V
DDM3IO
and V
25M3
Power-on Sequence . . . . . 65
Freescale Semiconductor