MSC8144 Freescale Semiconductor, MSC8144 Datasheet - Page 37

• Manufacturer Part Number: MSC8144
• Description: Quad Core Digital Signal Processor
• Manufacturer: Freescale Semiconductor

Table 23 summarizes the reset actions that occur as a result of the different reset sources.
Freescale Semiconductor
Power-on reset
(PORESET)
External hard
reset (HRESET)
External soft reset
(SRESET)
Host reset
command through
the TAP
Software
watchdog reset
RapidIO reset
Software hard
reset
Software soft reset
Configuration pins sampled (Refer to
Section 2.7.3.2 for details).
PLL state reset
Select reset configuration source
System reset configuration write
HRESET driven
IPBus modules reset (TDM, UART, SWT,
DDRC, IPBus master, GIC, HS, and GPIO)
SRESET driven
Extended cores reset
CLASS registers reset
Timers, Performance Monitor
Packet Processor, PCI, DMA
Name
Reset Action/Reset Source
Input/ Output
Input/ Output
Direction
Internal
Internal
Internal
Internal
Internal
Input
MSC8144 Quad Core Digital Signal Processor Data Sheet, Rev. 1
Table 23. Reset Actions for Each Reset Source
Initiates the soft reset flow. The MSC8144 detects an external assertion of SRESET only if it occurs
Initiates the power-on reset flow that resets the MSC8144 and configures various attributes of the
MSC8144. On PORESET, the entire MSC8144 device is reset. All PLLs states is reset, HRESET
and SRESET are driven, the extended cores are reset, and system configuration is sampled. The
reset source and word are configured only when PORESET is asserted.
Initiates the hard reset flow that configures various attributes of the MSC8144. While HRESET is
asserted, SRESET is also asserted. HRESET is an open-drain pin. Upon hard reset, HRESET and
SRESET are driven, the extended cores are reset, and system configuration is sampled. Note that
the RCW (reset Configuration Word) is not reloaded during HRESET assertion after out of power on
reset sequence. The reset configuration word is described in the Reset chapter in the MSC8144
Reference Manual.
while the MSC8144 is not asserting reset. SRESET is an open-drain pin. Upon soft reset, SRESET is
driven, the extended cores are reset, and system configuration is maintained.
When a host reset command is written through the Test Access Port (TAP), the TAP logic asserts the
soft reset signal and an internal soft reset sequence is generated.
When the MSC8144 watchdog count reaches zero, a software watchdog reset is signalled. The
enabled software watchdog event then generates an internal hard reset sequence.
When the RapidIO logic asserts the RapidIO hard reset signal, it generates an internal hard reset
sequence.
A hard reset sequence can be initialized by writing to a memory mapped register (RCR)
A soft reset sequence can be initialized by writing to a memory mapped register (RCR)
Power-On Reset
External only
(PORESET)
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Table 22. Reset Sources
Hard Reset (HRESET)
(Software Watchdog,
Software or RapidIO)
External or Internal
Yes
Yes
Yes
Yes
Yes
Yes
Yes
No
No
No
No
Description
External or
Software
registers
registers
internal
Some
Most
Yes
Yes
Yes
No
No
No
No
No
No
Soft Reset (SRESET)
Electrical Characteristics
Depends on command
EXTEST, CLAMP, or
JTAG Command:
Some registers
Most registers
HIGHZ
Yes
Yes
No
No
No
No
No
No
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