MSC8144 Freescale Semiconductor, MSC8144 Datasheet - Page 61

• Manufacturer Part Number: MSC8144
• Description: Quad Core Digital Signal Processor
• Manufacturer: Freescale Semiconductor

2.7.12
Table 49
Figure 36
Figure 37
the rising edge of the clock, these AC timing diagrams also apply when the falling edge is the active edge.
Figure 37
Figure 38
Freescale Semiconductor
SPI outputs valid—Master mode (internal clock) delay
SPI outputs hold—Master mode (internal clock) delay
SPI outputs valid—Slave mode (external clock) delay
SPI outputs hold—Slave mode (external clock) delay
SPI inputs—Master mode (internal clock input setup time
SPI inputs—Master mode (internal clock input hold time
SPI inputs—Slave mode (external clock) input setup time
SPI inputs—Slave mode (external clock) input hold time
Notes:
1. Output specifications are measured from the 50 percent level of the rising edge of CLKIN to the 50 percent level of the signal.
2. The symbols for timing specifications follow the pattern of t
Timings are measured at the pin.
and t
(NI) for the time SPICLK clock reference (K) goes to the high state (H) until outputs (O) are invalid (X).
(first two letters of functional block)(reference)(state)(signal)(state)
provides the SPI input and output AC timing specifications.
provides the AC test load for the SPI.
through
shows the SPI timings in slave mode (external clock).
shows the SPI timings in master mode (internal clock).
Note: The clock edge is selectable on SPI.
Output Signals:
SPICLK (Input)
SPI Timing
Input Signals:
(See Note)
(See Note)
Figure 38
SPIMOSI
SPIMISO
Output
Characteristic
represent the AC timings from
MSC8144 Quad Core Digital Signal Processor Data Sheet, Rev. 1
Figure 37. SPI AC Timing in Slave Mode (External Clock)
t
NEIVKH
Table 50. SPI AC Timing Specifications
Figure 36. SPI AC Test Load
Z
0
= 50 Ω
Table
t
NEKHOX
for outputs. For example, t
(first two letters of functional block)(signal)(state) (reference)(state)
t
NEIXKH
49. Note that although the specifications generally reference
Symbol
t
t
t
t
t
t
NEKHOV
NEKHOX
t
t
NIKHOV
NIKHOX
NEIVKH
NEIXKH
NIIVKH
NIIXKH
R
L
= 50 Ω
2
1
NIKHOX
OV
Min
0.5
2
4
0
4
2
DD
symbolizes the internal timing
/2
Max
6
8
for inputs
Unit
ns
ns
ns
ns
ns
ns
ns
ns
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