MSC8144 Freescale Semiconductor, MSC8144 Datasheet
MSC8144
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MSC8144 Summary of contents
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... DSP cores. This document contains information on a product under development. Freescale reserves the right to change or discontinue this product without notice. © Freescale Semiconductor, Inc., 2007. All rights reserved. Document Number: MSC8144 MSC8144 FC-PBGA–783 29 mm × – The two Ethernet controllers support 10/100/1000 Mbps ...
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... Product Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77 7 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78 List of Figures Figure 1. MSC8144 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . 3 Figure 2. StarCore SC3400 DSP Core Subsystem Block Diagram 3 Figure 3. MSC8144 FC-PBGA Package, Top View . . . . . . . . . . . . 4 Figure 4. MSC8144 FC-PBGA Package, Bottom View . . . . . . . . . 5 Figure 5. SerDes Reference Clocks Input Stage . . . . . . . . . . . . . 31 Figure 6. Overshoot/Undershoot Voltage for V Figure 7 ...
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... Debug Support Instruction Cache OCE30 DPU P-bus SC3400 Xa-bus Core Xb-bus Figure 2. StarCore SC3400 DSP Core Subsystem Block Diagram MSC8144 Quad Core Digital Signal Processor Data Sheet, Rev. 1 Freescale Semiconductor 10 Mbytes M3 Memory Controller 128-bit at 400 MHz CLASS QUICC Engine Subsystem Serial RapidIO ...
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... Pin Assignments and Reset States 1 Pin Assignments and Reset States This section includes diagrams of the MSC8144 package ball grid array layouts and tables showing how the pinouts are allocated for the package. 1.1 FC-PBGA Ball Layout Diagrams Top and bottom views of the FC-PBGA package are shown in Figure 3 and Figure 4 with their ball location index numbers. ...
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... T MSC8144 Figure 4. MSC8144 FC-PBGA Package, Bottom View MSC8144 Quad Core Digital Signal Processor Data Sheet, Rev. 1 Freescale Semiconductor Bottom View ...
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... B5 GND B6 GE_MDC B7 GND SXC 1 B8 Reserved 1 B9 Reserved MSC8144 Quad Core Digital Signal Processor Data Sheet, Rev Table 1. Signal List by Ball Number I/O Multiplexing Mode On 0 (000) 1 (001) 2 (010) 3 (011) Ethernet 2 Ethernet 2 Ethernet 2 SGMII support on SERDES is enabled by Reset Configuration Word SGMII support on SERDES is enabled by Reset Configuration Word ...
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... GND RIOPLL 1 C18 Reserved C19 V DDSXP C20 SRIO_TXD2/GE1_SGMII_T X MSC8144 Quad Core Digital Signal Processor Data Sheet, Rev. 1 Freescale Semiconductor I/O Multiplexing Mode On 0 (000) 1 (001) 2 (010) 3 (011) SGMII support on SERDES is enabled by Reset Configuration Word SGMII support on SERDES is enabled by Reset Configuration Word Ethernet 2 ...
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... D24 MDQ23 D25 V DDDDR D26 MDQ22 D27 MDQ21 MDQS2 D28 1 E1 Reserved MSC8144 Quad Core Digital Signal Processor Data Sheet, Rev I/O Multiplexing Mode On 0 (000) 1 (001) 2 (010) 3 (011) SGMII support on SERDES is enabled by Reset Configuration Word Ethernet 2 TDM PCI TDM PCI ...
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... F3 V DDGE1 F4 GE1_TD3/UTP_TD5/ PCI_AD30 F5 GE1_TD1/UTP_TD3/ PCI_AD28 F6 GND F7 GE1_TD0/UTP_TD2/ PCI_AD27 F8 V DDGE1 F9 GND MSC8144 Quad Core Digital Signal Processor Data Sheet, Rev. 1 Freescale Semiconductor I/O Multiplexing Mode On 0 (000) 1 (001) 2 (010) 3 (011) UTOPIA Ethernet 1 PCI UTOPIA Ethernet 1 PCI UTOPIA Ethernet 1 PCI UTOPIA Ethernet 1 ...
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... G16 GND G17 V DD G18 GND G19 V DD G20 GND 1 G21 Reserved G22 GND MSC8144 Quad Core Digital Signal Processor Data Sheet, Rev I/O Multiplexing Mode On 0 (000) 1 (001) 2 (010) 3 (011) UTOPIA Ethernet 1 UTOPIA Ethernet 1 PCI UTOPIA Ethernet 1 UTOPIA Ethernet 1 PCI — ...
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... J1 Reserved J2 GND J3 V DDIO J4 STOP_BS 4 J5 NMI_OUT 4 J6 INT_OUT SDA/GPIO27 MSC8144 Quad Core Digital Signal Processor Data Sheet, Rev. 1 Freescale Semiconductor I/O Multiplexing Mode On 0 (000) 1 (001) 2 (010) 3 (011) UART/GPIO/IRQ GPIO/ Ethernet PCI IRQ 1 PCI Ethernet 1 I2C/GPIO 2 4 (100) ...
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... V DD K16 V DD K17 V DD K18 GND K19 V DD K20 GND K21 V DD K22 V DDDDR MSC8144 Quad Core Digital Signal Processor Data Sheet, Rev I/O Multiplexing Mode On 0 (000) 1 (001) 2 (010) 3 (011) 2 Supply 4 (100) 5 (101) 6 (110) 7 (111 Freescale Semiconductor Ref ...
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... L27 V DDDDR L28 MCK1 1 M1 Reserved M2 TRST M3 EE0 M4 EE1 M5 UTP_RCLK/PCI_AD13 M6 UTP_RADDR0/PCI_AD7 M7 UTP_TD8/PCI_AD30 MSC8144 Quad Core Digital Signal Processor Data Sheet, Rev. 1 Freescale Semiconductor I/O Multiplexing Mode On 0 (000) 1 (001) 2 (010) 3 (011) UTOPIA TMR/ UTOPIA GPIO TIMER/GPIO TIMER/GPIO I UART/GPIO/IRQ UTOPIA PCI UTOPIA PCI ...
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... V DD N16 V DDM3 N17 V DD N18 V DDM3 N19 V DD N20 V DDM3 N21 GND MSC8144 Quad Core Digital Signal Processor Data Sheet, Rev I/O Multiplexing Mode On 0 (000) 1 (001) 2 (010) 3 (011) UTOPIA PCI Power UTOPIA PCI UTOPIA PCI TIMER/GPIO 2 Supply 4 (100) 5 (101) ...
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... P27 GND P28 MCK2 1 R1 Reserved R2 TCK R3 TDO R4 UTP_RD12/PCI_AD16 R5 UTP_RCLAV_PDRPA/ PCI_AD12 R6 UTP_RADDR4/PCI_AD11 MSC8144 Quad Core Digital Signal Processor Data Sheet, Rev. 1 Freescale Semiconductor I/O Multiplexing Mode On 0 (000) 1 (001) 2 (010) 3 (011) UTOPIA PCI UTOPIA PCI UTOPIA PCI GPIO/IRQ PCI GPIO/IRQ PCI UTOPIA ...
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... T13 GND T14 GND T15 GND T16 GND T17 GND T18 GND T19 GND T20 GND MSC8144 Quad Core Digital Signal Processor Data Sheet, Rev I/O Multiplexing Mode On 0 (000) 1 (001) 2 (010) 3 (011) UTOPIA PCI UTOPIA PCI UTOPIA PCI UTOPIA PCI ...
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... U27 MDQ1 U28 MDQ0 1 V1 Reserved V2 UTP_TD10/PCI_CBE0 V3 UTP_TADDR3 V4 UTP_TD1/PCI_PERR V5 UTP_TADDR0/PCI_AD23 V6 UTP_TADDR1/PCI_AD24 V7 UTP_TCLAV/PCI_AD28 MSC8144 Quad Core Digital Signal Processor Data Sheet, Rev. 1 Freescale Semiconductor I/O Multiplexing Mode On 0 (000) 1 (001) 2 (010) 3 (011) UTOPIA PCI UTOPIA PCI UTOPIA PCI UTOPIA PCI UTOPIA PCI UTOPIA ...
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... W16 V DDM3 W17 GND W18 V 25M3 W19 GND W20 V DDM3 W21 GND W22 GND MSC8144 Quad Core Digital Signal Processor Data Sheet, Rev I/O Multiplexing Mode On 0 (000) 1 (001) 2 (010) 3 (011) UTOPIA PCI UTOPIA PCI UTOPIA PCI UTOPIA PCI UTOPIA PCI ...
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... UTP_TD13/PCI_CBE3 AA3 TDM5RSYN/PCI_AD15 GPIO10 AA4 TDM5TD3, AT/PCI_AD17/ 6 GPIO11 AA5 TDM5RCLK/PCI_AD13 GPIO28 AA6 GND MSC8144 Quad Core Digital Signal Processor Data Sheet, Rev. 1 Freescale Semiconductor I/O Multiplexing Mode On 0 (000) 1 (001) 2 (010) 3 (011) UTOPIA PCI TDM/GPIO TDM TDM TDM UTOPIA PCI ...
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... AB12 GND AB13 V DDM3 AB14 GND AB15 V DDM3 AB16 GND AB17 V DDM3 AB18 GND MSC8144 Quad Core Digital Signal Processor Data Sheet, Rev I/O Multiplexing Mode On 0 (000) 1 (001) 2 (010) 3 (011) TDM TDM TDM/GPIO/ IRQ TDM/GPIO TDM/GPIO/IRQ TDM/GPIO/IRQ TDM TDM 2 4 (100) ...
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... V DDDDR AC26 MECC0 AC27 V DDDDR AC28 ECC_MDQS 1 AD1 Reserved 3, 6 AD2 GPIO1 AD3 TMR0/GPIO13 MSC8144 Quad Core Digital Signal Processor Data Sheet, Rev. 1 Freescale Semiconductor I/O Multiplexing Mode On 0 (000) 1 (001) 2 (010) 3 (011) UTOPIA UTOPIA TDM TDM/GPIO/IRQ TDM/GPIO/IRQ TDM PCI TIMER/GPIO 2 4 (100) ...
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... AE12 GND 1 AE13 Reserved AE14 GND 1 AE15 Reserved 1 AE16 Reserved 1 AE17 Reserved AE18 GND MSC8144 Quad Core Digital Signal Processor Data Sheet, Rev I/O Multiplexing Mode On 0 (000) 1 (001) 2 (010) 3 (011) GPIO GPIO/IRQ/SPI_SCK 2 4 (100) 5 (101) 6 (110) 7 (111) TDM TDM TDM ...
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... GND AF26 V DDDDR AF27 GND AF28 V DDDDR 1 AG1 Reserved 3, 6 AG2 GPIO16/IRQ0 AG3 TDM0TCLK MSC8144 Quad Core Digital Signal Processor Data Sheet, Rev. 1 Freescale Semiconductor I/O Multiplexing Mode On 0 (000) 1 (001) 2 (010) 3 (011) GPIO/IRQ/SPI_MOSI GPIO/IRQ 2 4 (100) 5 (101) 6 (110) 7 (111) TDM TDM ...
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... Reserved 1 AH11 Reserved 1 AH12 Reserved 1 AH13 Reserved 1 AH14 Reserved 1 AH15 Reserved 1 AH16 Reserved MSC8144 Quad Core Digital Signal Processor Data Sheet, Rev I/O Multiplexing Mode On 0 (000) 1 (001) 2 (010) 3 (011) GPIO/IRQ/SPI_SL GPIO/IRQ/SPI_MISO 2 4 (100) 5 (101) 6 (110) 7 (111) TDM TDM TDM TDM ...
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... Internal 20 KΩ pull-up resistor. 6. For signals with GPIO functionality, the open-drain and internal 20 KΩ pull-up resistor can be configured by GPIO register programming. See Chapter 23, GPIO of the MSC8144 Reference Manual for configuration details. 2 Electrical Characteristics This document contains detailed information on power considerations, DC/AC electrical characteristics, and AC timing specifications ...
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... Section 3.5, Thermal Considerations includes a formula for computing the chip junction temperature (T 4. PLL supply voltage is specified at input of the filter and not at pin of the MSC8144 (see Figure 46) MSC8144 Quad Core Digital Signal Processor Data Sheet, Rev Table 2. Absolute Maximum Ratings ...
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... Operating temperature range: • Standard • Extended Note: PLL supply voltage is specified at input of the filter and not at pin of the MSC8144 (see Figure 46). 2.3 Default Output Driver Characteristics Table 4 provides information on the characteristics of the output driver strengths. The values are preliminary estimates. Driver Type ...
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... Thermal resistance between the active surface of the die and the case top surface determined by the cold plate method (MIL SPEC-883 Method 1012.1) with the calculated case temperature. Section 3.5, Thermal Considerations provides a detailed explanation of these characteristics. 2.5 Power Characteristics The estimated typical power dissipation for MSC8144 versus the core frequency is shown in Table 6. Extended Core Frequency 266 333 400 ...
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... This section describes the DC electrical specifications for the DDR SDRAM interface of the MSC8144. Note: DDR SDRAM uses V DDDDR 2.6.1.1 DDR2 (1.8 V) SDRAM DC Electrical Characteristics Table 8 provides the recommended operating conditions for the DDR2 SDRAM component(s) of the MSC8144 when (typ DDDDR Table 8. DDR2 SDRAM DC Electrical Characteristics for V Parameter/Condition ...
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... Input/output capacitance: DQ, DQS, DQS Delta input/output capacitance: DQ, DQS, DQS Note: This parameter is sampled. V DDDDR 2.6.1.2 DDR (2.5V) SDRAM DC Electrical Characteristics Table 10 provides the recommended operating conditions for the DDR SDRAM component(s) of the MSC8144 when (typ DDDDR Table 10. DDR SDRAM DC Electrical Characteristics for V Parameter/Condition 1 ...
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... SRIO_REF_CLK/ SRIO_REF_CLK is designed to work with a spread spectrum clock (0 to 0.5% spreading at 3033 kHz rate is allowed), assuming both ends have same reference clock. For better results use a source without significant unintended modulation. MSC8144 Quad Core Digital Signal Processor Data Sheet, Rev. 1 Freescale Semiconductor . The reference clock must be able to drive this termination. The ...
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... Signal input current, Output high voltage –1.6 mA, OH Output low voltage 0.4mA OL Pin Capacitance Note: Not tested. Guaranteed by design. 2.6.5 UART DC Electrical Characteristics TBD MSC8144 Quad Core Digital Signal Processor Data Sheet, Rev conditions . Table 13. PCI DC Electrical Characteristics Symbol V DDPCI ...
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... Signal high input current 2 Output high voltage –1 mA, OH Output low voltage Input Pin Capacitance Note: Not tested. Guaranteed by design. MSC8144 Quad Core Digital Signal Processor Data Sheet, Rev. 1 Freescale Semiconductor Electrical Characteristics Symbol Min Max V 3.135 3.465 DDGE1 V DDGE2 V 2 ...
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... Tri-state (high impedance off state) leakage current Signal low input current 0 Signal high input current 2 Output high voltage –2 mA, OH except open drain pins MSC8144 Quad Core Digital Signal Processor Data Sheet, Rev Symbol V DDIO ...
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... Figure 7). 32 cycles should be accounted only after V CLKIN and PCI_CLK_IN should either be stable low during the power- • power-up or should swing within V during power-up. Figure 7 shows a sequence in which V MSC8144 Quad Core Digital Signal Processor Data Sheet, Rev. 1 Freescale Semiconductor Symbol DDIO Must not exceed 10% of clock period reaches its nominal value ...
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... Software soft reset All MSC8144 reset sources are fed into the reset controller, which takes different actions depending on the source of the reset. The reset status register indicates the most recent sources to cause a reset. Table 22 describes the reset sources. MSC8144 Quad Core Digital Signal Processor Data Sheet, Rev. 1 ...
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... Reference Manual. External soft reset Input/ Output Initiates the soft reset flow. The MSC8144 detects an external assertion of SRESET only if it occurs (SRESET) while the MSC8144 is not asserting reset. SRESET is an open-drain pin. Upon soft reset, SRESET is driven, the extended cores are reset, and system configuration is maintained. ...
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... MHz <= CLKIN < 133 MHz 3 Delay from HRESET deassertion to SRESET deassertion • REFCLK = 25 MHz to 133 MHz Note: Timings are not tested, but are guaranteed by design. MSC8144 Quad Core Digital Signal Processor Data Sheet, Rev must be asserted externally for at least 32 PORESET STOP_BS 2 C EEPROM. ...
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... MDQS[n] and any corresponding bit that is CISKEW captured with MDQS[n]. Subtract this value from the total timing budget recommended operating conditions with V MSC8144 Quad Core Digital Signal Processor Data Sheet, Rev. 1 Freescale Semiconductor RCW_SRC2,RCW_SRC1,RCW_SRC0,STOP_BS and RCFG_CLKIN_RNG pins must be valid 2 ...
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... DQSS override bits in the TIMING_CFG_2 register. This will typically be set to the same delay as the clock adjust in the CLK_CNTL register. The timing parameters listed in the table assume that these 2 parameters have been set to the same adjustment value. See the MSC8144 Reference Manual for a description and understanding of the timing modifications enabled by use of these bits. ...
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... Figure 9 shows the DDR SDRAM output timing for the MCK[n] MCK[n] MDQS MDQS Figure 10 shows the DDR SDRAM output timing diagram. MCK[n] MCK[n] ADDR/CMD Write A0 MDQS[n] MDQ[x] MSC8144 Quad Core Digital Signal Processor Data Sheet, Rev. 1 Freescale Semiconductor to skew measurement (t MCK MDQS t MCK t DDKHMHmax DDKHMH(min) = –0.6 ns Figure 9 ...
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... Table 26. SDn_REF_CLK and SDn_REF_CLK AC Requirements Parameter Description Symbol REFCLK cycle time t REF REFCLK cycle-to-cycle t REFCJ jitter Phase jitter t REFPJ MSC8144 Quad Core Digital Signal Processor Data Sheet, Rev Ω Ω Figure 11. DDR AC Test Load Min Typical Max Units — ...
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... A passive high pass filter network placed at the receiver. This is often referred to as passive equalization. • The use of active circuits in the receiver. This is often referred to as adaptive equalization. MSC8144 Quad Core Digital Signal Processor Data Sheet, Rev. 1 Freescale Semiconductor Differential Peak-Peak = 2 × (A – B) ...
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... Unit Interval Table 29. Short Run Transmitter AC Timing Specifications—3.125 GBaud Characteristic Output Voltage, Differential Output Voltage Deterministic Jitter Total Jitter Multiple output skew Unit Interval MSC8144 Quad Core Digital Signal Processor Data Sheet, Rev Range Symbol Unit Min Max V –0.40 2 ...
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... The output eye pattern of an LP-Serial transmitter that implements pre-emphasis (to equalize the link and reduce inter-symbol interference) need only comply with the transmitter output compliance mask when pre-emphasis is disabled or minimized. MSC8144 Quad Core Digital Signal Processor Data Sheet, Rev. 1 Freescale Semiconductor Range ...
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... Table 34. Receiver AC Timing Specifications—1.25 GBaud Characteristic Differential Input Voltage Deterministic Jitter Tolerance Combined Deterministic and Random Jitter Tolerance MSC8144 Quad Core Digital Signal Processor Data Sheet, Rev Time min (mV) ...
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... Table 36. Receiver AC Timing Specifications—3.125 GBaud Characteristic Differential Input Voltage Deterministic Jitter Tolerance Combined Deterministic and Random Jitter Tolerance Total Jitter Tolerance Multiple Input Skew MSC8144 Quad Core Digital Signal Processor Data Sheet, Rev. 1 Freescale Semiconductor Range Symbol Unit Min Max J ...
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... Figure 15 with the parameters specified in Table 37. The eye pattern of the receiver test signal is measured at the input pins of the receiving device with the device replaced with a 100 Ω ± 5% differential resistive load. MSC8144 Quad Core Digital Signal Processor Data Sheet, Rev Range Symbol Unit ...
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... AC coupling and the compliance template centered at 0 Volts differential. The left and right edges of the template shall be aligned with the mean zero crossing points of the measured data eye. The load for this test shall be 100 Ω ± resistive 5% differential to 2.5 GHz. MSC8144 Quad Core Digital Signal Processor Data Sheet, Rev. 1 Freescale Semiconductor – B ...
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... Input timings are measured at the pin. 5. The reset assertion timing requirement for HRESET is in Table 24 and Figure 8 MSC8144 Quad Core Digital Signal Processor Data Sheet, Rev Table 38. PCI AC Timing Specifications 33 MHz Symbol ...
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... Input Figure 17. PCI Input AC Timing Measurement Conditions Figure 18 shows the PCI output AC timing conditions. Output Delay High-Impedance Output Figure 18. PCI Output AC Timing Measurement Condition MSC8144 Quad Core Digital Signal Processor Data Sheet, Rev. 1 Freescale Semiconductor = 50 Ω Figure 16. PCI AC Test Load ...
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... Note: For some TDM modes receive data and receive sync are being input on other pins. This timing is valid for them as well. See the MSC8144 Reference Manual. Figure 20 shows TDMxTSYN AC timing in TSO=0 mode. TDMxTCLK t TDMVKH TDMxTSYN Figure 21 shows the TDM Output AC timing MSC8144 Quad Core Digital Signal Processor Data Sheet, Rev Table 39. TDM Timing Symbol t TDMC t TDMCH ...
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... TDMxTCLK TDMxTDAT TDMxTSYN Note: For some TDM modes transmit data is being output on other pins. This timing is valid for it as well. See the MSC8144 Reference Manual 2.7.8 UART Timing Characteristics URXD and UTXD inputs high/low duration URXD and UTXD inputs rise/fall time UTXD output rise/fall time ...
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... This section describes the AC electrical characteristics for the Ethernet interface. There are programmable delay units (PDU) that should be programmed differently for each Interface to meet timing. There is a general configuration register 4 (GCR4) used to configure the timing. For additional information, see the MSC8144 Reference Manual. ...
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... Figure 26 shows the MII transmit AC timing diagram. TX_CLK TXD[3:0] TX_EN TX_ER 2.7.10.3 MII Receive AC Timing Specifications Table 44 provides the MII receive AC timing specifications. Table 44. MII Receive AC Timing Specifications Parameter/Condition RX_CLK duty cycle MSC8144 Quad Core Digital Signal Processor Data Sheet, Rev. 1 Freescale Semiconductor t MDC t MDCH t t MDDVKH MDDXKH t MDKHDX ) for 10 Mbps is 400 ns and for 100 Mbps ...
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... Typical REF_CLK clock period ( RMX Notes: 1. Typical REF_CLK clock period (t 2. Program GCR4 as 0x00001405 MSC8144 Quad Core Digital Signal Processor Data Sheet, Rev for 10 Mbps is 400 ns and for 100 Mbps Ω Figure 27. AC Test Load t ...
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... Typical REF_CLK clock period is 8ns 2. Measured using load. 3. Measured using load 4. REF_CLK duty cycle is TBD. 5. Program GCR4 as 0x00002008 Figure 31 provides the AC test load. MSC8144 Quad Core Digital Signal Processor Data Sheet, Rev. 1 Freescale Semiconductor t RMX t t RMXF RMXH t RMTKHDX ...
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... Data to clock input skew (at receiver) 3 Clock cycle duration 4, 5 Duty cycle for 1000Base-T Duty cycle for 10BASE-T and 100BASE-TX Rise time (20%–80%) Fall time (20%–80%) GTX_CLK125 reference clock period MSC8144 Quad Core Digital Signal Processor Data Sheet, Rev SMDVKH Valid t SMXR Valid Figure 31 ...
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... Transmitter) TXD[8:5][3:0] TXD[7:4][3:0] TX_CTL TX_CLK (At PHY) RXD[8:5][3:0] RXD[7:4][3:0] RX_CTL RX_CLK (At PHY) Figure 32. RGMII AC Timing and Multiplexing s MSC8144 Quad Core Digital Signal Processor Data Sheet, Rev. 1 Freescale Semiconductor of 2.5 V +/- 5%. DD scales to 400 ns +/- 40 ns and 40 ns +/- 4 ns, respectively. /2. t RGTH t SKEWT TXD[8:5] TXD[3:0] ...
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... Figure 34. UTOPIA AC Timing (External Clock) Figure 35 shows the UTOPIA timing with internal clock. UTOPIA CLK (output) t UIIVKH Input Signals: UTOPIA Output Signals: UTOPIA Figure 35. UTOPIA AC Timing (Internal Clock) MSC8144 Quad Core Digital Signal Processor Data Sheet, Rev Symbol Min t 1 UEKHOV t 1 UEKHOX ...
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... Note) Note: The clock edge is selectable on SPI. Figure 37. SPI AC Timing in Slave Mode (External Clock) Figure 38 shows the SPI timings in master mode (internal clock). MSC8144 Quad Core Digital Signal Processor Data Sheet, Rev. 1 Freescale Semiconductor Table 50. SPI AC Timing Specifications Symbol t NIKHOV ...
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... GPIO in valid to REFCLK edge (GPIO in set-up time) REFCLK edge to GPIO in not valid (GPIO in hold time) Figure 39 shows the GPIO timing. REFCLK t GPKHOZ GPIO (Output) GPIO (Input) MSC8144 Quad Core Digital Signal Processor Data Sheet, Rev NIIXKH t NIIVKH t NIKHOX Table 51. GPIO Timing Symbol ...
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... All timings apply to OnCE module data transfers as well as any other transfers via the JTAG port. Figure 41 Shows the Test Clock Input Timing Diagram TCK (Input) t TCKR MSC8144 Quad Core Digital Signal Processor Data Sheet, Rev. 1 Freescale Semiconductor Table 52. EE Pin Timing Symbol Type Asynchronous Synchronous to Core clock pins ...
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... TDI TMS (Input) TDO (Output) TDO (Output) Figure 44 Shows the TRST timing diagram. TRST (Input) t TRST MSC8144 Quad Core Digital Signal Processor Data Sheet, Rev BSVKH Input Data Valid t TCKHOV Output Data Valid t TCKHOZ Figure 42. Boundary Scan (JTAG) Timing t TDIVKH ...
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... This is an acceptable exception to the rule during start-up. However, each such input can draw per input pin per MSC8144 device in the system during start-up. An assertion of the inputs to the high voltage level before power-up should be with slew rate less than 4V/ns. ...
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... GND indicates using a 10 kΩ pull-down resistor (recommended direct connection to the ground plane. Direct connections to the ground plane may yield DC current up to 50mA through the I/O supply that adds to overall power consumption. MSC8144 Quad Core Digital Signal Processor Data Sheet, Rev input. The filter Ω resistor in series with two 2.2 μF, DDPLL inputs ...
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... Note: If the DDR controller is not used, disable the internal DDR clock by writing the CLK11DIS bit in the System Clock Control Register (SCCR[CLK!11DIS]). See Chapter 7, Clocks, in the MSC8144 Reference Manual for details. MSC8144 Quad Core Digital Signal Processor Data Sheet, Rev. 1 Freescale Semiconductor ...
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... When the error code corrected mechanism is not used in any 32- or 16-bit DDR configuration, refer to Table 56 to determine the correct pin connections. Table 56. Connectivity of Unused ECC Mechanism Pins Signal Name MECC[0–7] ECC_MDM ECC_MDQS ECC_MDQS MSC8144 Quad Core Digital Signal Processor Data Sheet, Rev Pin connection in use pull- DDDDR in use pull-down to GND ...
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... GND RIOPLL GND SXP GND SXC V DDSXP V DDSXC Note: The x indicates the lane number {0,1,2,3} for all unused lanes. MSC8144 Quad Core Digital Signal Processor Data Sheet, Rev. 1 Freescale Semiconductor Hardware Design Considerations Pin Connection GND GND GND GND GND GND NC NC ...
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... Hardware Design Considerations 3.3.3 M3 Memory Related Pins Table 59. Connectivity of M3 Related Pins When M3 Memory Is Not Used Signal Name M3_RESET V 25M3 V DDM3 V DDM3IO MSC8144 Quad Core Digital Signal Processor Data Sheet, Rev Pin Connection NC GND GND GND Freescale Semiconductor ...
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... Table 61. Connectivity of GE1 Related Pins When only a subset of the GE1 Interface Is required Signal Name GE1_COL GE1_CRS GE1_RD[0–3] GE1_RX_ER GE1_RX_CLK GE1_RX_DV GE1_SGMII_RX GE1_SGMII_RX GE1_SGMII_TX MSC8144 Quad Core Digital Signal Processor Data Sheet, Rev. 1 Freescale Semiconductor Hardware Design Considerations is DDGE1 Pin Connection ...
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... V is tied to either 2 3.3 B. DDGE2 Table 63. Connectivity of GE1 Related Pins When only a subset of the GE1 Interface Is required Signal Name GE2_RD[0-3] GE2_RX_CLK GE2_RX_DV GE2_RX_ER GE2_SGMII_RX MSC8144 Quad Core Digital Signal Processor Data Sheet, Rev Pin Connection NC NC GND tied DDGE2 ...
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... UTP_TCLK UTP_TD[0–15] UTP_TEN UTP_TPRTY UTP_TSOC V DDIO MSC8144 Quad Core Digital Signal Processor Data Sheet, Rev. 1 Freescale Semiconductor lists the recommended management pin connections. Table 65 assumes that the alternate function of the specified pin is not used. If Hardware Design Considerations Pin Connection GND ...
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... PCI_DEVSEL PCI_FRAME PCI_GNT PCI_IDS PCI_IRDY PCI_PAR PCI_PERR PCI_REQ PCI_SERR PCI_STOP PCI_TRDY V DDIO MSC8144 Quad Core Digital Signal Processor Data Sheet, Rev Table 66 for those signals that are not selected. Pin Connection GND GND GND GND GND GND 3.3 V Table 67 assumes that the alternate function of the ...
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... V DDIO Note: When using I/O multiplexing mode tie the TDM7TSYN/PCI_AD4 signal (ball number AC9) to GND. Note: For details on configuration, see the MSC8144 Reference Manual. For additional information, refer to the MSC8144 Design Checklist (AN3202). 3.4 External DDR SDRAM Selection TBD MSC8144 Quad Core Digital Signal Processor Data Sheet, Rev. 1 ...
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... I/O The power dissipation values for the MSC8144 are listed in Table 5. The ambient temperature for the device is the air temperature in the immediate vicinity that would cool the device. The junction-to-ambient thermal resistances are JEDEC standard values that provide a quick and easy estimation of thermal performance. There are two values in common usage: the value determined on a single layer board and the value obtained on a board with two planes ...
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... MSC8144 Reference Manual (MSC8144RM). Includes functional descriptions of the extended cores and all the internal subsystems including configuration and programming information. • Application Notes. Cover various programming topics related to the StarCore DSP core and the MSC8144 device. • SC3400 DSP Core Reference Manual. Covers the SC3400 core architecture, control registers, clock registers, program control, and instruction set. • ...
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... Updates JTAG timings in • Clarifies connectivity guidelines for Ethernet pins in Section 3.3.4. • Miscellaneous pin connectivity guidelines were updated in • Updates name of core subsystem reference manual. MSC8144 Quad Core Digital Signal Processor Data Sheet, Rev Table 69. Document Revision History Description Table 20 ...
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... MSC8144 Quad Core Digital Signal Processor Data Sheet, Rev. 1 Freescale Semiconductor Revision History 79 ...
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... P.O. Box 5405 Denver, Colorado 80217 1-800-441-2447 or 303-675-2140 Fax: 303-675-2150 LDCForFreescaleSemiconductor@hibbertgroup.com Document Number: MSC8144 Rev. 1 5/2007 Information in this document is provided solely to enable system and software implementers to use Freescale Semiconductor products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document ...