MSC7115 Motorola Semiconductor Products, MSC7115 Datasheet - Page 35

• Manufacturer Part Number: MSC7115
• Manufacturer: Motorola Semiconductor Products

2.5.10
Figure 20 shows the signal behavior of the
2.5.11
Figure 21 shows the signal behavior of the
Freescale Semiconductor
Notes:
Notes:
Number
Number
601
602
603
604
67
68
1.
2.
3.
1.
2.
3.
4.
5.
6.
Event Timing
GPIO Timing
Refer to Table 24 for a definition of the APBCLK period.
Direction of the EVNT signal is configured through the GPIO and Event port registers.
Refer to the MSC711x Reference Manual for details on EVNT pin functionality.
Refer to Table 24 for a definition of the APBCLK period.
Direction of the GPIO signal is configured through the GPIO port registers.
Refer to MSC711x Reference Manual for details on GPIO pin functionality.
GPI data is synchronized to the APBCLK internally and the minimum listed is the capability of the hardware to capture data
into a register when the GPA_DR is read. The specification is not tested due to the asynchronous nature of the input and
dependence on the state of the DSP core. It is guaranteed by design.
The input and output signals cannot toggle faster than 50 MHz.
Level-sensitive interrupts should be held low until the system determines (via the service routine) that the interrupt is
acknowledged.
EVNT as input
EVNT as output
GPI
GPO
Port A edge-sensitive interrupt
Port A level-sensitive interrupt
4.5
5
MSC7115 Low-Cost 16-bit DSP with DDR Controller Data Sheet, Rev. 11
Characteristics
Characteristics
EVNT out
EVNT in
GPO
GPI
Table 27. GPIO Signal Timing
EVNT
GPI/GPO
Figure 21. GPI/GPO Pin Timing
Table 26. EVNT Signal Timing
Figure 20. EVNT Pin Timing
pin.
pin.
Synchronous to core clock
Synchronous to core clock
Asynchronous
Asynchronous
Asynchronous
Asynchronous
Type
Type
1,2,3
602
601
68
67
1.5 × APBCLK periods
1.5 × APBCLK periods
1.5 × APBCLK periods
3 × APBCLK periods
1 APBCLK period
1 APBCLK period
Min
Min
6
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