MSC7115 Motorola Semiconductor Products, MSC7115 Datasheet - Page 22

• Manufacturer Part Number: MSC7115
• Manufacturer: Motorola Semiconductor Products

Specifications
2.5.2.5
The core clock can also be limited by the frequency range of the DDR devices in the system. Table 14 summarizes this
restriction.
2.5.3
The MSC7115 device has several inputs to the reset logic. All MSC7115 reset sources are fed into the reset controller, which
takes different actions depending on the source of the reset. The reset status register indicates the most recent sources to cause
a reset. Table 15 describes the reset sources.
Table 16 summarizes the reset actions that occur as a result of the different reset sources.
22
Note:
Power-on reset
(PORESET)
External Hard
reset (HRESET)
Software
watchdog reset
Bus monitor
reset
JTAG EXTEST,
CLAMP, or
HIGHZ command
DDR 200 (PC-1600)
DDR 266 (PC-2100)
DDR 333 (PC-2600)
CLKCTRL[CKSEL]
DDR Type
Name
This table results from the allowed range for F
11
11
01
01
Reset Timing
Core Clock Frequency Range When Using DDR Memory
Input/ Output
Direction
Allowed Frequency
Internal
Internal
Internal
Range for DDR CK
Input
MSC7115 Low-Cost 16-bit DSP with DDR Controller Data Sheet, Rev. 11
CLKCTRL[RNG]
83–100 MHz
83–133 MHz
83–150 MHz
Table 13. Resulting Ranges Permitted for the Core Clock
1
0
1
0
Table 14. Core Clock Ranges When Using DDR
Initiates the power-on reset flow that resets the MSC7115 and configures various attributes of the
MSC7115. On PORESET, the entire MSC7115 device is reset. SPLL and DLL states are reset,
HRESET is driven, the SC1400 extended core is reset, and system configuration is sampled. The
system is configured only when PORESET is asserted.
Initiates the hard reset flow that configures various attributes of the MSC7115. While HRESET is
asserted, HRESET is an open-drain output. Upon hard reset, HRESET is driven and the SC1400
extended core is reset.
When the MSC7115 watchdog count reaches zero, a software watchdog reset is signalled. The
enabled software watchdog event then generates an internal hard reset sequence.
When the MSC7115 bus monitor count reaches zero, a bus monitor hard reset is asserted. The
enabled bus monitor event then generates an internal hard reset sequence.
When a Test Access Port (TAP) executes an EXTEST, CLAMP, or HIGHZ command, the TAP logic
asserts an internal reset signal that generates an internal soft reset sequence.
Resulting
Division
Factor
Table 15. Reset Sources
166 ≤ core clock ≤ 200 MHz
166 ≤ core clock ≤ 266 MHz
166 ≤ core clock ≤ 300 MHz
1
2
2
4
OUT
Corresponding Range
for the Core Clock
, which depends on clock selected via CLKCTRL[CKSEL].
150 ≤ Core_Clk ≤ 200 MHz
150 ≤ Core_Clk ≤ 200 MHz
75 ≤ Core_Clk ≤ 150 MHz
Allowed Range
of Core Clock
Reserved
Description
Core limited to 2 × maximum DDR frequency
Core limited to 2 × maximum DDR frequency
Core limited to 2 × maximum DDR frequency
Reserved
Limited by range of PLL
Limited by range of PLL
Limited by range of PLL
Comments
Freescale Semiconductor
Comments