MSC7115 Motorola Semiconductor Products, MSC7115 Datasheet - Page 29

• Manufacturer Part Number: MSC7115
• Manufacturer: Motorola Semiconductor Products

Figure 10 and Figure 11 show HDI16 read signal timing. Figure 12 and Figure 13 show HDI16 write signal
timing.
Freescale Semiconductor
Notes:
No.
1.
2.
3.
4.
5.
6.
7.
8.
9.
10. The host request is HREQ/HREQ in the single host request mode and HRRQ/HRRQ and HTRQ/HTRQ in the double host
11. Compute the value using the expression.
12. For mask set 1M88B, the read and write data strobe minimum deassertion width for non-”last data register” accesses in single
T
In the timing diagrams below, the controls pins are drawn as active low. The pin polarity is programmable.
V
The read data strobe is HRD/HRD in the dual data strobe mode and HDS/HDS in the single data strobe mode.
For 64-bit transfers, The “last data register” is the register at address 0x7, which is the last location to be read or written in data
transfers. This is RX0/TX0 in the little endian mode (HBE = 0), or RX3/TX3 in the big endian mode (HBE = 1).
This timing is applicable only if a read from the “last data register” is followed by a read from the RXL, RXM, or RXH registers
without first polling RXDF or HREQ bits, or waiting for the assertion of the HREQ/HREQ signal.
This timing is applicable only if two consecutive reads from one of these registers are executed.
The write data strobe is HWR in the dual data strobe mode and HDS in the single data strobe mode.
The data strobe is host read (HRD/HRD) or host write (HWR/HWR) in the dual data strobe mode and host data strobe
(HDS/HDS) in the single data strobe mode.
request mode. HRRQ/HRRQ is deasserted only when HOTX fifo is empty, HTRQ/HTRQ is deasserted only if HORX fifo is full
(treat as level Host Request).
and dual data strobe modes is based on timings 57 and 58.
HCLK
DD
= 3.3 V ± 0.15 V; T
HRRQ (double host request)
HREQ (single host request)
= 2/ (Core Clock). At 200 MHz, T
MSC7115 Low-Cost 16-bit DSP with DDR Controller Data Sheet, Rev. 11
Characteristics
Table 22. Host Interface (HDI16) Timing
Figure 10. Read Timing Diagram, Single Data Strobe
J
HCS[1–2]
HD[0–15]
= –40°C to +105 °C, C
HA[0–3]
HRW
HDS
3
57
HCLK
= 10 ns. T
49
L
= 30 pF for maximum delay timings and C
57
55
CORE
50
53
44a
= core clock period. At 266 MHz, T
Expression
Mask Set 1L44X
51
58
1, 2
(continued)
61
52
Value
56
58
44c
L
= 0 pF for minimum delay timings.
Expression
Mask Set 1M88B
CORE
= 3.75 ns.
Value
Unit
29