MSC7115 Motorola Semiconductor Products, MSC7115 Datasheet - Page 23

• Manufacturer Part Number: MSC7115
• Manufacturer: Motorola Semiconductor Products

2.5.3.1
Asserting
external power to the MSC7115 reaches at least 2/3
2.5.3.2
The MSC7115 has two mechanisms for writing the reset configuration:
Five signal levels (see Chapter 1 for signal description details) are sampled on
operating conditions:
2.5.3.3
Table 17 and Figure 4 describe the reset timing for a reset configuration write.
Freescale Semiconductor
Configuration pins sampled (refer to Section 2.5.3.1 for
details).
PLL and clock synthesis states Reset
HRESET Driven
Software watchdog and bus time-out monitor registers
Clock synthesis modules (STOPCTRL, HLTREQ, and
HLTACK) reset
Extended core reset
Peripheral modules reset
Note:
No.
•
•
•
•
•
•
1
2
From a host through the host interface (HDI16)
From memory through the I
BM[0–1]
SWTE
H8BIT
HDSP
PORESET
Timings are not tested, but are guaranteed by design.
Required external PORESET duration minimum
Delay from PORESET deassertion to HRESET deassertion
Reset Action/Reset Source
Power-On Reset (PORESET) Pin
Reset Configuration
Reset Timing Tables
initiates the power-on reset flow.
MSC7115 Low-Cost 16-bit DSP with DDR Controller Data Sheet, Rev. 11
Table 17. Timing for a Reset Configuration Write
Table 16. Reset Actions for Each Reset Source
2
C interface
Characteristics
V
DD
PORESET
.
Power-On Reset
External only
(PORESET)
must be asserted externally for at least 16
Yes
Yes
Yes
Yes
Yes
Yes
Yes
PORESET
Internal (Software
Watchdog or Bus
Hard Reset
External or
(HRESET)
Monitor)
Yes
Yes
Yes
Yes
Yes
No
No
deassertion to define the boot and
Expression
521/F
16/F
CLKIN
CLKIN
EXTEST, CLAMP,
JTAG Command:
CLKIN
Soft Reset
(SRESET)
or HIGHZ
Specifications
Yes
Yes
Yes
Yes
No
No
No
cycles after
clocks
clocks
Unit
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