MSC7115 Motorola Semiconductor Products, MSC7115 Datasheet - Page 25

• Manufacturer Part Number: MSC7115
• Manufacturer: Motorola Semiconductor Products

2.5.4.2
Table 19 and Table 20 list the output AC timing specifications and measurement conditions for the DDR DRAM interface.
Freescale Semiconductor
Notes:
No.
200
204
205
206
207
208
209
210
211
212
CK cycle time, (CK/CK crossing)
• 100 MHz (DDR200)
• 133 MHz (DDR266)
An/RAS/CAS/WE/CKE output setup with respect to
CK
An/RAS/CAS/WE/CKE output hold with respect to CK
CSn output setup with respect to CK
CSn output hold with respect to CK
CK to DQSn
Dn/DQMn output setup with respect to DQSn
Dn/DQMn output hold with respect to DQSn
DQSn preamble start
DQSn epilogue end
1.
2.
3.
4.
5.
All CK/CK referenced measurements are made from the crossing of the two signals ±0.1 V.
t
arrives 75–125% of a DRAM cycle after the write command is issued. Any skew between DQSn and CK must be considered
when trying to achieve this 75%–125% goal. The TCFG2[WRDD] bits can be used to shift DQSn by 1/4 DRAM cycle
increments. The skew in this case refers to an internal skew existing at the signal connections. By default, the CK/CK crossing
occurs in the middle of the control signal (An/RAS/CAS/WE/CKE) tenure. Setting TCFG2[ACSM] bit shifts the control signal
assertion 1/2 DRAM cycle earlier than the default timing. This means that the signal is asserted no earlier than 410 ps before
the CK/CK crossing and no later than 677 ps after the crossing time; the device uses 1087 ps of the skew budget (the interval
from –410 to +677 ps). Timing is verified by referencing the falling edge of CK. See Chapter 10 of the MSC711x Reference
Manual for details.
Determined by maximum possible skew between a data strobe (DQS) and any corresponding bit of data. The data strobe
should be centered inside of the data eye.
Please note that this spec is in reference to the DQSn first rising edge. It could also be referenced from CK(r), but due to
programmable delay of the write strobes (TCFG2[WRDD]), there pre-amble may be extended for a full DRAM cycle. For this
reason, we reference from DQSn.
All outputs are referenced to the rising edge of CK. Note that this is essentially the CK/DQSn skew in spec 208. In addition
there is no real “maximum” time for the epilogue end. JEDEC does not require this is as a device limitation, but simply for the
chip to guarantee fast enough write to read turn-around times. This is already guaranteed by the memory controller operation.
DDKHMH
DDR DRAM Output AC Timing Specifications
2
can be modified through the TCFG2[WRDD] DQSS override bits. The DRAM requires that the first write data strobe
MSC7115 Low-Cost 16-bit DSP with DDR Controller Data Sheet, Rev. 11
5
Parameter
4
1
Table 19. DDR DRAM Output AC Timing
3
3
Symbol
t
t
t
t
t
t
t
t
t
t
t
DDKHMH
DDKHDS,
DDKHDX,
DDKHCS
DDKHCX
DDKHMP
DDKHME
DDKHAS
DDKHAX
DDKLDS
DDKLDX
t
CK
0.25 × t
0.5 × t
0.5 × t
0.5 × t
0.5 × t
Not applicable
0.25 × t
–0.25 × t
Mask Set
1L44X
–600
1050
–600
CK
CK
CK
CK
10
CK
MCK
– 2250
– 1250
– 2250
– 1250
– 1050
CK
–
Min
0.5 × t
0.5 × t
0.5 × t
0.5 × t
0.25 × t
0.25 × t
–0.25 × t
Mask Set
1M88B
–600
–600
7.52
CK
CK
CK
CK
1.0
CK
CK
– 1000
– 1000
– 1000
– 1000
– 750
– 750
CK
Max
Specifications
600
600
—
—
—
—
—
—
—
—
—
Unit
ns
ns
ps
ps
ps
ps
ps
ps
ps
ps
ps
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