MSC7115 Motorola Semiconductor Products, MSC7115 Datasheet - Page 24

• Manufacturer Part Number: MSC7115
• Manufacturer: Motorola Semiconductor Products

Specifications
2.5.4
This section provides the AC electrical characteristics for the DDR DRAM interface.
2.5.4.1
Table 18 provides the input AC timing specifications for the DDR DRAM interface.
24
Notes:
No.
201
202
Note: DQS centering is done internally.
—
—
AC input low voltage
AC input high voltage
Maximum Dn input setup skew relative to DQSn
input
Maximum Dn input hold skew relative to DQSn
input
1.
2.
3.
PORESET
PORESET
Output (I/O)
HRESET
Maximum possible skew between a data strobe (DQSn) and any corresponding bit of data (D[8n + {0...7}] if 0 ≤ n ≤ 7).
See Table 19 for t
Dn should be driven at the same time as DQSn. This is necessary because the DQSn centering on the DQn data tenure is
done internally.
DDR DRAM Controller Timing
DQSn
Internal
DDR DRAM Input AC Timing Specifications
Dn
Input
MSC7115 Low-Cost 16-bit DSP with DDR Controller Data Sheet, Rev. 11
Parameter
Figure 4. Timing Diagram for a Reset Configuration Write
1
CK
value.
Figure 5. DDR DRAM Input Timing Diagram
Configuration Pins
are sampled
Table 18. DDR DRAM Input AC Timing
202
201
D0
Symbol
V
V
—
—
IH
IL
D1
202
V
2
201
REF
Min
—
—
—
+ 0.31
V
V
Mask Set
REF
DDM
1L44X
1026
386
– 0.31
+ 0.3
Max
Freescale Semiconductor
V
V
Mask Set
REF
1M88B
DDM
900
900
– 0.31
+ 0.3
Unit
ps
ps
V
V