MSC7115 Motorola Semiconductor Products, MSC7115 Datasheet - Page 19

• Manufacturer Part Number: MSC7115
• Manufacturer: Motorola Semiconductor Products

2.4
This section describes the DC electrical characteristics for the MSC7115.
Note:
Table 6 lists the DDR DRAM capacitance.
Freescale Semiconductor
Core and PLL voltage
DRAM interface I/O voltage
I/O voltage
DRAM interface I/O reference voltage
DRAM interface I/O termination voltage
Input high CLKIN voltage
DRAM interface input high I/O voltage
DRAM interface input low I/O voltage
Input leakage current, V
V
Tri-state (high impedance off state) leakage current,
V
Signal low input current, V
Signal high input current, V
Output high voltage, I
Output low voltage, I
Typical core power
• at 200 MHz
• at 266 MHz (mask set 1M88B only)
Notes:
Input/output capacitance: DQ, DQS
Delta input/output capacitance: DQ, DQS
Note:
REF
IN
= V
input leakage current
DDIO
The leakage current is measured for nominal voltage values must vary in the same direction (for example, both
and
1.
2.
3.
4.
5.
These values were measured under the following conditions:
• V
• f = 1 MHz
• T
• V
• V
A
DDM
OUT
OUT
V
DC Electrical Characteristics
= 25°C
DDC
The value of V
V
exceed ±2% of the DC value.
V
to V
Output leakage for the memory interface is measured with all outputs disabled, 0 V ≤ V
The core power values were measured.using a standard EFR pattern at typical conditions (25°C, 200 MHz or 266 MHz, 1.2 V
core).
REF
TT
= V
(peak to peak) = 0.2 V
= 2.5 V ± 0.125 V
5
REF
is not applied directly to the MSC7115 device. It is the level measured at the far end signal termination. It should be equal
vary by +2 percent or both vary by –2 percent).
OL
Characteristic
must be equal to 50% of V
DDM
OH
. This rail should track variations in the DC level of V
= 5 mA
IN
= –2 mA, except open drain pins
/2
IL
= V
MSC7115 Low-Cost 16-bit DSP with DDR Controller Data Sheet, Rev. 11
IH
1
= 0.4 V
= 2.0 V
DDM
DDIO
Parameter/Condition
at the MSC7115 device must remain within 50 mV of V
2
3
Table 5. DC Electrical Characteristics
DDM
Table 6. DDR DRAM Capacitance
and track V
Symbol
V
DDM
V
V
V
V
I
V
V
DDPLL
V
VTT
VREF
V
IHCLK
V
DDIO
I
P
DDC
DDM
I
REF
I
IHM
OZ
I
ILM
IN
OH
H
OL
L
C
variations as measured at the receiver. Peak-to-peak noise must not
REF
0.49 × V
.
V
V
REF
REF
2.375
3.135
Min
1.14
–0.3
–1.0
–1.0
–1.0
–1.0
2.4
2.0
—
—
—
—
+ 0.28
– 0.04
DDM
DDM
at the DRAM device at all times.
Symbol
Typical
V
V
GND
C
1.25
0.09
0.09
0.09
0.09
222
293
C
1.2
2.5
3.3
3.0
3.0
DDM
REF
—
OUT
DIO
0
IO
≤ V
DDM
.
0.51 × V
V
V
V
Max
REF
REF
DDM
30
30
2.625
3.465
3.465
Max
1.26
0.4
—
—
—
1
5
1
1
1
+ 0.04
– 0.18
+ 0.3
DDM
Specifications
Unit
pF
pF
Unit
V
mW
mW
µA
µA
µA
µA
µA
V
V
V
V
V
V
V
V
V
V
DDIO
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