HD49351BP Renesas Electronics Corporation., HD49351BP Datasheet - Page 7

• Manufacturer Part Number: HD49351BP
• Description: Cds/pga & 10-bit A/d Tg Converter
• Manufacturer: Renesas Electronics Corporation.

HD49351BP/HBP
3. Automatic Offset Calibration Function and Black-Level Clamp Data Settings
4. DC Offset Compensation Feedback Function
Table 1 Loop Gain Multiplication Factor during
5. Pre-Blanking Function
Rev.1.0, Jul 06, 2004, page 7 of 28
The DAC DC voltage added to the output of the PGA amplifier is adjusted by automatic offset calibration.
The data, which cancels the output offset of the PGA amplifier and the input offset of the ADC, and the clamp data
(14 LSB to 76 LSB) set by register are added and input to the DAC.
The automatic offset calibration starts automatically after the RESET mode set by register is cancelled and
terminates after 40,000 clock cycles (when fclk = 40.0 MHz, 1.0 ms, fclk = 20.0 MHz, 2.0 ms).
Feedback is done to set the black signal level input during the OB period to the DC standard, and all offsets
(including the CCD offset and the CDSAMP offset) are compensated for.
The offset from the ADC output is calculated during the OB period, and SHAMP feedback capacitor C3 is charged
by the current DAC (see figure 1).
The open-loop differential gain (∆Gain/∆H) per 1 H of the feedback loop is given by the following equation. 1H is
the one cycle of the OBP.
When the PGAMP gain setting is changed, the high-speed lead-in operation state is entered, and the feedback loop
gain is increased by a multiple of N. Loop gain multiplication factor N can be selected from 4 times, 8 times, 16
times, or 32 times by changing the register settings (see table 1). Note that the open-loop differential gain
(∆Gain/∆H) must be one or lower. If it is two or more, oscillation occurs.
The time from the termination of high-speed lead-in operation to the return of normal loop gain operation can be
selected from 1 H, 2 H, 4 H, or 8 H. If the offset error is over 16 LSB, the high-speed lead-in operation continues,
and when the offset error is 16 LSB or less, the operation returns to the normal loop-gain operation after 1 H, 2 H, 4
H, or 8 H depending on the register settings. (Refer to table 2.)
During the PBLK input period, the CDS input operation is separated and protected from the large input signal. The
ADC digital output is fixed to clamp data (14 to 76 LSB).
[0]
H
H
∆Gain/∆H = 0.078/(fclk × C3) (fclk: ADCLK frequency, C3: SHAMP external feedback capacitor)
Example: When fclk = 20 MHz and C3 = 1.0 µF, ∆Gain/∆H = 0.0039
DC offset compensation per 1 H (LSB) = 0.0039 × Offset error (LSB)
Note: There is a maximum value in the above-mentioned amount of offset errors.
L
L
(register settings)
High-Speed Lead-In Operation
HGain-Nsel
[1]
H
H
L
L
Multiplication
Factor N
16
32
4
8
Table 2 High-Speed Lead-In Operation
[0]
H
H
L
L
(register settings)
Cancellation Time
HGstop-Hsel
Note)
[1]
H
H
L
L
Cancellation
Time
1 H
2 H
4 H
8 H