HD49351BP Renesas Electronics Corporation., HD49351BP Datasheet - Page 11

• Manufacturer Part Number: HD49351BP
• Description: Cds/pga & 10-bit A/d Tg Converter
• Manufacturer: Renesas Electronics Corporation.

HD49351BP/HBP
Detailed Timing Specifications
Detailed Timing Specifications when CDS_in Input Mode is Used
Figure 3 shows the detailed timing specifications when the CDS_in input mode is used, and table 8 shows each timing
specification.
Table 8
No.
(1)
(2)
(3)
(4)
(5)
(6)
(7), (8)
(9)
(10)
OBP Detailed Timing Specifications
Figure 4 shows the OBP detailed timing specifications.
The OB period is from the fifth to the twelfth clock cycle after the OB pulse is inputted. The average of the black
signal level is taken for eight input cycles during the OB period and it becomes the clamp level (DC standard).
Rev.1.0, Jul 06, 2004, page 11 of 28
Timing
Black-level signal fetch time
SP1 ‘Hi’ period
Signal-level fetch time
SP2 ‘Hi’ period
SP1 falling to SP2 falling time
SP1 falling to ADCLK rising inhibit time
ADCLK t
ADCLK rising to digital output
ADCLK rising to digital output delay time
Timing Specifications when the CDS_in Input Mode is Used
WH
CDS_in
OBP
Note:
min./t
Figure 3 Detailed Timing Chart when CDS_in Input Mode is Used
1. Shifts 1 clock cycle depending on the OBP input timing.
CDS_in
SP1
SP2
ADCLK
D0 to D9
WL
min
N
Figure 4 OBP Detailed Timing Specifications
OB pulse > 2 clock cycles
holding time
N+1
(2)
Black
level
(7)
(1)
(5)
Signal
OB period *
level
(4)
(6)
Symbol
t
t
t
t
t
t
t
t
t
CDS1
CDS2
CDS3
CDS4
CDS5
CDS6
CDS7, 8
CHLD9
COD10
N+5
(8)
(3)
1
Min
—
Typ × 0.8
—
Typ × 0.8
Typ × 0.85
—
11
—
—
(9)
(10)
N+12
Typ
(1.5)
1/4f
(1.5)
1/4f
1/2f
(5)
—
(7)
(16)
Vth
Vth
Vth
CLK
CLK
CLK
N+13
Max
—
Typ × 1.2
—
Typ × 1.2
Typ × 1.15
—
—
—
—
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns