HD49351BP Renesas Electronics Corporation., HD49351BP Datasheet - Page 2

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HD49351BP

Manufacturer Part Number
HD49351BP
Description
Cds/pga & 10-bit A/d Tg Converter
Manufacturer
Renesas Electronics Corporation.
Datasheet

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
HD49351BP
Manufacturer:
RENESAS/瑞萨
Quantity:
20 000
HD49351BP/HBP
Pin Arrangement
Pin Description
BGA
Pin No.
K1
J1
H1 to D2
C1
C2, C3
B1
A1
A2
B2
A3
B3
B4
A4
B5
A5
B6
A6
B7
B8
A7
Rev.1.0, Jul 06, 2004, page 2 of 28
3 to 12
14
PAD
No.
1
2
13
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
Notes: 1.
Symbol
ID
DVss1, 2
D0 to D9
DVdd2
Dvss3
CLK_in
HD_in
VD_in
Reset
RG
DVdd3
DVdd4
H1
1/2clk_o
Dvss4
Dvss4
H2
1/4clk_o
DVdd4
DVdd3
2.
3.
Pin 41 outputs the STROB, pin 39 outputs the SUB_SW when pin 61 is Low.
Pin 41 inputs the Vgate, pin 39 inputs the ADCK when pin 61 is High.
1/2 and 4clk output terminal becomes 1/3 and 1/6clk output respectively,
when operating TG in 3 divided mode.
Description
Odd/even number line detecting pulse output pin
CDS Digital ground + ADC output buffer ground (0V)
Digital output (D0; LSB, D9; MSB)
ADC output buffer power supply (3 V)
General ground for TG (0V)
VD input
Hardware reset (for DLL reset)
Reset gate pulse output
General power supply for TG (3V)
H1,2 buffer power supply (3 V)
H.CCD transfer pulse output-1
H1,2 buffer ground (0 V)
H1,2 buffer ground (0 V)
H.CCD transfer pulse output-2
H1,2 buffer power supply (3 V)
General power supply for TG (3 V)
CLK input (max 72 MHz)
HD input
CLK_in 2 divided output. 3 divided output at 3 divided mode
CLK_in 4 divided output. 6 divided output at 3 divided mode
G
A
B
C
D
E
H
K
F
J
XSUB
SUB_PD
DVss3
VRM
CH2
VRB
VRT
XV3
XV4
Bias
10
32
33
35
38
40
42
45
46
48
47
ADC_in
BLKC
SUB_SW
Strob
AVdd
AVss
CH1
CH3
CH4
XV2
31
34
36
37
39
41
43
44
49
50
9
DVdd4
CDS_in
AVdd
XV1
30
28
52
51
8
DVdd3
1/4clk
BLKFB
AVss
29
27
55
53
7
(Top view)
DVss4
BLKSH
test2
H2
26
25
56
54
6
1/2clk
DVss4
DLLC
test1
24
23
57
58
5
DVdd4
DVdd1
MON
H1
22
21
59
60
4
DVdd3
Sdata
DVss3
41cont
RG
19
20
14
61
63
3
VD_i/o
CDS_CS
Reset
DVss3
SCK
D9
D7
D6
D4
D2
17
18
14
12
10
62
64
2
9
7
5
CLK_in
DVdd2
DVss1,2
HD_i/o
D8
D5
D3
D1
D0
16
15
13
11
ID
1
8
6
4
3
2
1
I/O
O
O
I
I
I
I
O
O
O
O
O
Analog(A) or
Digital(D)
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
Remarks
2 mA/10 pF
2 mA/10 pF
Schmitt trigger
3 mA/10 pF
30 mA/165 pF
2 mA/10 pF
30 mA/165 pF
2 mA/10 pF

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