HD49351BP Renesas Electronics Corporation., HD49351BP Datasheet

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... HD49351BP/HBP CDS/PGA & 10-bit A/D TG Converter Description The HD49351BP/HBP is a CMOS IC that provides CDS-PGA analog processing (CDS/PGA) suitable for CCD camera digital signal processing systems together with a 10-bit A/D converter and timing generator in a single chip. HD49351 has deleted the stripe mode, pd_mix There are address map and timing generator charts besides this specification ...

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... HD49351BP/HBP Pin Arrangement Notes: 1. Pin 41 outputs the STROB, pin 39 outputs the SUB_SW when pin 61 is Low. 2. Pin 41 inputs the Vgate, pin 39 inputs the ADCK when pin 61 is High. 3. 1/2 and 4clk output terminal becomes 1/3 and 1/6clk output respectively, when operating divided mode ...

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... HD49351BP/HBP Pin Description (cont.) BGA PAD Pin No. No. Symbol Description A8 30 XV1 V.CCD transfer pulse output XV2 V.CCD transfer pulse output-2 A10 32 XV3 V.CCD transfer pulse output-3 B10 33 XV4 V.CCD transfer pulse output CH1 Read out pulse output-1 C10 ...

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... HD49351BP/HBP Input/Output Equivalent Circuit Pin Name Digital output D0 to D9, RG, H1A to H2B, XV1 to XV4, CH1 to CH4, XSUB, SUB_SW, SUB_PD, STROB, MON Digital input ADCLK, OBP, CPDM, SP1,2, PBLK, CS, SCK, SDATA, CLK_in, HD_in, VD_in Analog CDS_in ADC_in BLKSH, BLKFB, BLKC VRT, VRM, VRB BIAS Rev ...

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... HD49351BP/HBP Block Diagram SUB_SW SUB_PD STROB ADC_in CDS_in CDS BLKSH BLKC DC offset BLKFB compensation circuit Rev.1.0, Jul 06, 2004, page Timing generator DLL 10bit PGA ADC Serial Bias interface generator AVss DVss1 to 4 Reset ...

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... HD49351BP/HBP Internal Functions Functional Description • CDS input  CCD low-frequency noise is suppressed by CDS (correlated double sampling).  The signal level is clamped at 14 LSB to 76 LSB (set by resister: 5 bit 2 LSB step controls) during the OB 1 period. *  Gain can be adjusted using 8 bits of register (0.132 dB steps) within the range from –2. 31.40 dB. * • ...

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... HD49351BP/HBP 3. Automatic Offset Calibration Function and Black-Level Clamp Data Settings The DAC DC voltage added to the output of the PGA amplifier is adjusted by automatic offset calibration. The data, which cancels the output offset of the PGA amplifier and the input offset of the ADC, and the clamp data (14 LSB to 76 LSB) set by register are added and input to the DAC ...

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... HD49351BP/HBP 6. ADC Digital Output Control Function The ADC digital output includes the functions output enable, code conversion, and test mode. Tables 3, 4 and 5 show the output functions and the codes. Table 3 ADC Digital Output Functions Hi Hi-Z L ...

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... HD49351BP/HBP 7. Adjustment of Black-Level S/H Response Frequency Characteristics The CR time constant that is used for sampling/hold (S/H) at the black level can be adjusted by changing the register settings, as shown in table 6. Table 6 SHSW CR Time Constant Setting [0] [1] [ Time Constant (Typ) 2.20 nsec (cutoff frequency conversion) (72 MHz) [0] [1] ...

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... HD49351BP/HBP Timing Chart Figure 2 shows the timing chart when CDS_in and ADC_in input modes are used When CDS_in input mode is used N CDS_in SP1 SP2 ADCLK When ADC_in input mode is used N+1 N ADC_in ADCLK Figure 2 Output Timing Chart when CDS_in and ADC_in Input Modes are Used • ...

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... HD49351BP/HBP Detailed Timing Specifications Detailed Timing Specifications when CDS_in Input Mode is Used Figure 3 shows the detailed timing specifications when the CDS_in input mode is used, and table 8 shows each timing specification. CDS_in SP1 SP2 ADCLK Figure 3 Detailed Timing Chart when CDS_in Input Mode is Used ...

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... HD49351BP/HBP Detailed Timing Specifications at Pre-Blanking Figure 5 shows the pre-blanking detailed timing specifications. PBLK Digital output (D0 to D9) Figure 5 Detailed Timing Specifications at Pre-Blanking Detailed Timing Specifications when ADC_in Input Mode is Used Figure 6 shows the detailed timing chart when ADC_in input mode is used, and table 9 shows each timing specification. ...

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... HD49351BP/HBP Dummy Clamp It adjusts the mis-clamp which occurs when taking the photo under the highlight conditions. (Like a sun) Normally it woks with the OB clamp, however when black level is out of the range caused by hightlight enter to OB part, it changes to clamp processing by dummy bit level. Resister settings are follows. ...

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... Unit °C °C BIAS Unit Test Conditions Remarks V 1 MHz LoPwr = low * HD49351HBP MHz LoPwr = high HD49351BP V All of digital input pin – µA DVdd = µ µ Vdd OH µ ...

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... HD49351BP/HBP Electrical Characteristics (cont.) • Items for CDS_in Input Mode Item Symbol Consumption current (1) I DD1 Consumption current (2) I DD2 CCD offset tolerance range V CCD Timing specifications (1) t CDS1 Timing specifications (2) t CDS2 Timing specifications (3) t CDS3 Timing specifications (4) t CDS4 ...

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... HD49351BP/HBP Serial Interface Specifications Timing Specifications t INT1 Latches SDATA at SCK rising edge CS SCK t su SDATA D8 D9 D10 D11 STD2(Upper data) Item Min Max f — 5 MHz SCK — INT1 — — ho The Kind of Data Data address has 256 type. H’00 to H’FF H’ ...

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... HD49351BP/HBP Explanation of Serial Data of CDS Part Serial data of CDS part are assigned to address H’F0 to H’F8. Functions are follows. Address • PGA gain ( address H’F0) Details are referred to page 6 block diagram. At CDS_in mode: –2. 0.132 dB × N (Log linear) At ADC_in mode: 0.57 times + 0.01784 times × ...

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... HD49351BP/HBP • Output mode ( address H’F1 and address H’ test mode. Combination details are page 8. Normally set to all 0. • SHA-fsel ( address H’F1 LPF switching of SH amplifier. Frequency characteristics are referred to page 9. To get rough idea, set the double cut off frequency point with using. • ...

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... HD49351BP/HBP Address • MON ( address H’F4) Select the pulse which output to pin MON (pin 60). When D0 to D2: 0, Fix to Low When 2, SP1 When 4, OBP When 6, CPDM • H12Baff ( address H’F4) Select the buffer size which output to pin H1A, H2A (pin 22, 26). ...

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... HD49351BP/HBP • Gray code (D8 to D12 of address H’F4) ADC output code can be change to following type by differential code gray SW (D9, D8). Binary code at D8: 0, Gray code at D8: 1 Normal at D9: 0, differential code at D9: 1 Differential code and gray code are recommended for this countermeasure. Figure 10 indicates circuit block. When luminance signal changes are smoothly, the number of bit of switching digital output bit can be reduced and easily to reduce the ripple using this function ...

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... HD49351BP/HBP Address Address • Address H’F5 sets the DLL delay time and selects the 1/4 phase. Details are on the next page. And D15 of address H’F8 can switch 2/3 divided mode but ensure that this address data relative to valid/invalid. ...

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... HD49351BP/HBP Address Address (3) Setting method of DLL 1. DLL step decides the how many divide the 1 cycle of sensor CLK. For reference, set 1 ns(when 2 ns DLL_current bit = 0, when 1 set to 1 ns) Can be set steps by 4 steps. Steps = ...

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... HD49351BP/HBP Operation Sequence at Power CLK_in Hardware Reset HD49351 serial data transfer SP1 SP2 Start control ADCLK of TG and OBP camera DSP etc. RESET bit Automatic offset calibration The following describes the above serial data transfer. For details of resistor settings are referred to serial data function table ...

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... HD49351BP/HBP Timing Specifications of High Speed Pulse H1, H2, RG waveform tr H2 90% 10 90% 10% RG twh Item min typ H1/ XV1 to 4 — — CH1 to 4 — — XSUB/SUB_SW — — two Item min typ H1/H2 overlap 12 20 Rev.1.0, Jul 06, 2004, page twh ...

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... HD49351BP/HBP Notice for Use 1. Careful handling is necessary to prevent damage due to static electricity. 2. This product has been developed for consumer applications, and should not be used in non-consumer applications this IC is sensitive to power line noise, the ground impedance should be kept as small as possible. Also, to prevent latchup, a ceramic capacitor of 0.1 µ ...

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... HD49351BP/HBP Example of Recommended External Circuit Slave mode Pin 57(Test1 = Low) 47 3.0V + 47/6 0 V.Baff CCD 33k 45 0.1 46 0 0.1 CCD signal input Master mode Pin 57(Test1 = Hi) 47 3.0V + 47/6 0 V.Baff CCD 33k 45 0.1 46 0 ...

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... HD49351BP/HBP CDS single operating mode Pin 56(Test2 = Low) Pin 57 is "Don't care" in this mode. 47 3.0V + 47/6 47 ADC_in 33k 0.1 0.1 0.1 47 0.1 CCD signal input Serial data when CDS single operation mode are following resister specifications. (Latch timing specification is same as normal mode INT1 SCK tsu ...

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... HD49351BP/HBP Package Dimensions 0. 0.15 S 0.08 S Rev.1.0, Jul 06, 2004, page 6.00 B 0.75 0.20 S Package Code JEDEC JEITA Mass (reference value) Unit 4.50 A area 0. Index Pin A 65 – 0.30 ± 0.05 0. Details of the part A TFBGA0606-65 — ...

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Keep safety first in your circuit designs! 1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead ...