HD49351BP Renesas Electronics Corporation., HD49351BP Datasheet - Page 22

• Manufacturer Part Number: HD49351BP
• Description: Cds/pga & 10-bit A/d Tg Converter
• Manufacturer: Renesas Electronics Corporation.

HD49351BP/HBP
• CDS_test (D12 of address H’F6)
• Dummy clamp current (D9 to 8 of address H’F7)
• Dummy clamp threshold (D12 to 10 of address H’F7)
Rev.1.0, Jul 06, 2004, page 22 of 28
1.
2.
3.
H1
DL_RG
DL_SP1
DL_SP2
DL_ADCLK
1
1
DLL step decides the how many divide the 1
cycle of sensor CLK. For reference,
set 1 ns(when 2 ns DLL_current bit = 0,
when 1 set to 1 ns)
Can be set 16 to 64 steps by 4 steps.
Recommended steps is clk_in = when 11 to 14 MHz: H'0E(60 steps)
Can be change each 4 type of pulse 0 to 15 steps with
1 step. (1 ns or 2 ns divide)
Select the 2 ns divide when sensor CLK is less than
15 MHz.
(3) Setting method of DLL
It is testing data. Normally set to 0.
Details are refer to page 13.
Details are refer to page 13.
Steps = 4 + (4
1
1
Data = When 0, 1/4
Data = When 0, off
1
1
0
Address
Address
10
1
1
When 2, 1/16
When 2, +64
When 4, +128
When 6, +192
14
N); possible to set N = 3 to 15
0
0
Default
1
1
28
when 14 to 22MHz: H'09(40 steps)
when 22 to 50MHz: H'1E(60 steps)
when 50 to 72MHz: H'19(40 steps)
1
1
42
Figure 15 Analog Delay (DLL) Circuit Block.
0
1
D7 D6 D5
D7 D6 D5
56
DL_RG_f
DL_SP2
When 1, 1/8
When 3, 1/32
When 1, +32
When 3, +96
When 5, +160
When 7, +224
STD1[7:0] (L)
STD1[7:0] (L)
D4 D3 D2
D4 D3 D2
(In phase with H1)
ADCLK(0)
P_ADCLK
DL_RG_r
DL_SP1
ADCLK
P_SP1
P_SP2
(0, 0)
D1 D0
D1 D0
DLL = 64 steps
DLL = 15 steps
DLL = 15 steps
DLL = 15 steps
DLL = 15 steps
(Rising)
(Falling)
STD2[15:8] (H)
STD2[15:8] (H)
CDS_test
Control voltage
D12 D11 D10 D9 D8
D12 D11 D10 D9 D8
AND
PC
DL_ADCLK
DL_SP1
DL_SP2
clamp th
Dummy
DL_ADCLK
DL_RG
clamp current
Dummy
DLL_C