HD49351BP Renesas Electronics Corporation., HD49351BP Datasheet - Page 23

• Manufacturer Part Number: HD49351BP
• Description: Cds/pga & 10-bit A/d Tg Converter
• Manufacturer: Renesas Electronics Corporation.

HD49351BP/HBP
Operation Sequence at Power On
Rev.1.0, Jul 06, 2004, page 23 of 28
V
CLK_in
Hardware
Reset
HD49351
serial data transfer
Start control
of TG and
camera DSP
RESET bit
Automatic offset
calibration
The following describes the above serial data transfer. For details of resistor settings are referred to serial data
function table.
DD
(1) Resistor transfer of TG part
(2) DLL data transfer of CDS part
(3) Reset=L of CDS part
(4) Reset=H of CDS part
(5) Other data of CDS part
Before transfer the Reset bit = 0, TG series pulse need to be settled, so address
H'00 to H'EF of TG part and H'F4 to H7F7 of CDS part should transfer in advance.
SP1
SP2
ADCLK
OBP
etc.
Figure 16 Operation Sequence at Power On
3clk or more
6clk or more
Must be stable within the operating
power supply voltage range
(1)
: Wait more than 6clk after release the hardware Reset and then transfer
: Transfer the phase data of RG, SP1, SP2, ADCLK of CDS part.
: Transfer Reset bit = 0 of address H'F2.
: Transfer Reset bit = 1 of address H'F2. (Reset release)
: Transfer the SH_SW_fsel and other PGA.
the necessary data to TG part.
(2) (3)
(Charge of external C)
CDS_Reset = Low
2ms or more
Note: At 2 divided mode: ADCLK = 1/2CLK_in
(4)
At 3 divided mode: ADCLK = 1/3CLK_in
Automatic adjustment taking
40,000ADCLK period after
Reset cancellation
40,000ADCLK or more
(offset calibration)
(5)