HD49351BP Renesas Electronics Corporation., HD49351BP Datasheet - Page 21

• Manufacturer Part Number: HD49351BP
• Description: Cds/pga & 10-bit A/d Tg Converter
• Manufacturer: Renesas Electronics Corporation.

HD49351BP/HBP
• Address H’F5 sets the DLL delay time and selects the 1/4 phase. Details are on the next page. And D15 of address
• Phase settings of high speed pulse (address H’F5 to H’F8)
Default Value of Each Phases
2 divided mode
3 divided mode
Note: 50% of duty pulse makes tr, tf of RG by DLL.
Rev.1.0, Jul 06, 2004, page 21 of 28
1
1
H’F8 can switch 2/3 divided mode but ensure that this address data relative to valid/invalid.
Divided mode
D0 to D7 of address H’F5
D0 to D14 of address H’F8
(1) Select the 1/4 phase from figure 13 at 2 divided mode (D15 = 0 of address H’F8).
(2) Then select the necessary delay time from figure 15.
1
1
Select the 1/6 phase from figure 14 at 3 divided mode (D15 = 1 of address H’F8).
·····P_SP1, P_SP2, P_ADCLK, P_RG
·····DL_SP1, DL_SP2, DL_RG, DL_ADCLK
RG can be set both of rising / falling edge optionally.
1
1
P_SP1
P_SP2
P_SP1
P_SP2
Address
Address
1
1
Figure 13 2 Divided Mode, 1/4 Phase Select (Valid at D15 = 0 of address H’F8)
Figure 14 3 Divided Mode, 1/6 Phase Select (Valid at D15 = 1 of address H’F8)
H1
H1
0
1
P_SP1
1
0
1
0
0
0
1
0
D15 of address H’F8 = 0
Select the 2 divided, 1/4 phase
Valid
Invalid
D7 D6 D5
P_RG
D6 D5
Data = 0
Data = 1
Data = 2
Data = 3
Data = 5
Data = 0
Data = 1
Data = 2
Data = 3
Data = 4
P_SP2
2
3
P_SP2
P_ADCLK
STD1[7:0] (L)
STD1[7:0] (L)
D4 D3 D2
D4
P_SP2
P_ADCLK
P_RG
P_ADCLK
P_RG
D2
P_SP1
D1 D0
D1 D0
H1
H1
P_SP1
P_ADCLK
1
1
2,3 divided
select
D15 D14 D13
D15 of address H’F8 = 1
Select the 3 divided, 1/6 phase
Invalid
Valid
P_RG
STD2[15:8] (H)
STD2[15:8] (H)
current
D12 D11 D10 D9 D8
D12
DLL
P_RG
0
5
Data = 0
Data = 1
Data = 2
Data = 3
Data = 0
Data = 1
Data = 2
Data = 3
Data = 4
Data = 5
D10
steps
P_ADCLK
DLL
D9 D8