N25Q128 Numonyx, N25Q128 Datasheet - Page 169

• Manufacturer Part Number: N25Q128
• Description: 128-mbit 3 V, Multiple I/o, 4-kbyte Subsector Erase On Boot Sectors, Xip Enabled, Serial Flash Memory With 108 Mhz Spi Bus Interface
• Manufacturer: Numonyx

Table 32.
1. tCH + tCL must be greater than or equal to 1/ fC.
2. Typical values given for TA = 25 °C
3. Value guaranteed by characterization, not 100% tested in production.
4. Expressed as a slew-rate.
5. Only applicable as a constraint for a WRSR instruction when SRWD is set to '1'.
6. VPPH should be kept at a valid level until the program or erase operation has completed and its result (success or failure)
7. When using the page program (PP) instruction to program consecutive bytes, optimized timings are obtained with one
8. int(A) corresponds to the upper integer part of A. For example int(12/8) = 2, int(32/8) = 4 int(15.3) =16.
tVPPHSL
tW
tCFSR
tWNVCR
tWVCR
tWRVECR
tPP
tSSE
tSE
tBE
Symbol
is known. Avoid applying VPPH to the W/VPP pin during Bulk Erase.
sequence including all the bytes versus several sequences of only a few bytes (1 < n < 256).
(7)
(6)
AC Characteristics (page 2 of 2)
Figure 102. Reset AC waveforms while a program or erase cycle is in progress
See
Reset
S
Alt.
Table 33.: Reset
Enhanced program supply voltage High
(VPPH) to Chip Select Low for Single and
Dual I/O Page Program
Write status register cycle time
Clear flag status register cycle time
Write non volatile configuration register
cycle time
Write volatile configuration register cycle
time
Write volatile enhanced
configurationregister cycle time
Page program cycle time (n bytes)
Program OTP cycle time (64 bytes)
Subsector erase cycle time
Sector erase cycle time
Bulk erase cycle time
Conditions.
Parameter
tSHRH
tRLRH
200
Min
tRHSL
1.3
40
0.2
40
40
int(n/8) ×
0.015
0.2
0.2
0.7
170
Typ
(8)
(2)
8
3
5
2
3
250
Max
AI06808
169/180
Unit
ms
ms
ms
ns
ns
ns
ns
s
s
s
s