N25Q128 Numonyx, N25Q128 Datasheet - Page 134
N25Q128
Manufacturer Part Number
N25Q128
Description
128-mbit 3 V, Multiple I/o, 4-kbyte Subsector Erase On Boot Sectors, Xip Enabled, Serial Flash Memory With 108 Mhz Spi Bus Interface
Manufacturer
Numonyx
Datasheet
1.N25Q128.pdf
(180 pages)
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9.3.3
Note:
134/180
DQ0
DQ3
DQ1
DQ2
C
S
Mode 3
Mode 0
Figure 71. Quad Command Fast Read instruction and data-out sequence QSP, EBh
Read OTP (ROTP)
The Read OTP (ROTP) instruction is used to read the 64 bytes OTP area in the QIO-SPI
protocol. The instruction functionality is exactly the same as the Read OTP instruction of the
Extended SPI protocol. The only difference is that in the QIO-SPI protocol instruction code,
address and output data are all parallelized on the four pins DQ0, DQ1, DQ2 and DQ3.
The dummy byte bits can not be parallelized: 8 clock cycles are requested to perform the
internal reading operation.
Instruction
0
1
A23-16 A15-8 A7-0
5
4
6
7
2
1
0
2
3
3
5
4
6
7
4
1
0
2
3
5
5
4
6
7
6
1
0
2
3
7
8
9 10
Dummy (ex.: 10)
15 16 17 18
Byte 1 Byte 2
IO switches from Input to Output
4
5
6
7
19
0
1
3
2
20
5
4
7
6
21
1
0
3
2
22
4
Byte 3 Byte 4
5
7
6
23
0
1
3
2
Quad_Command_Fast_Read_EBh
24
4
5
7
6
25 26 27
0
1
3
2
4
4
4
Byte 5 Byte 6
4
0
0
0
0
4
4
4
4
0
0
0
0