N25Q128 Numonyx, N25Q128 Datasheet - Page 116

• Manufacturer Part Number: N25Q128
• Description: 128-mbit 3 V, Multiple I/o, 4-kbyte Subsector Erase On Boot Sectors, Xip Enabled, Serial Flash Memory With 108 Mhz Spi Bus Interface
• Manufacturer: Numonyx

9.2.5
9.2.6
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Write Disable (WRDI)
The Write Disable (WRDI) instruction resets the Write Enable Latch (WEL) bit.
Apart form the parallelizing of the instruction code on the two pins DQ0 and DQ1, the
instruction functionality is exactly the same as the Write Disable (WRDI) instruction of the
Extended SPI protocol, please refer to
details.
Figure 46. Write Disable instruction sequence DIO-SPI
Dual Command Page Program (DCPP)
The Dual Command Page Program (DCPP) instruction allows to program the memory
content in DIO-SPI protocol, parallelizing the instruction code, the address and the input
data on two pins (DQ0 and DQ1). Before it can be accepted, a Write Enable (WREN)
instruction must previously have been executed. The Dual Command Page Program
(DCPP) instruction can be issued, when the device is set in DIO-SPI mode, by sending to
the memory indifferently one of the 3 instructions codes: 02h, A2h or D2h, the effect is
exactly the same. The 3 instruction codes are all accepted to help the application code
porting from Extended SPI protocol to DIO-SPI protocol.
Apart for the parallelizing on two pins of the instruction code, the Dual Command Page
Program instruction functionality is exactly the same as the Dual Input Extended Fast
Program of the Extended SPI protocol, please refer to
Fast Program
C
DQ0
DQ1
S
for further details.
0
Instruction
Section 9.1.10: Write Disable (WRDI)
1
2
Dual_Write_Disable
3
4
Section 9.1.13: Dual Input Extended
for further