N25Q128 Numonyx, N25Q128 Datasheet - Page 115
N25Q128
Manufacturer Part Number
N25Q128
Description
128-mbit 3 V, Multiple I/o, 4-kbyte Subsector Erase On Boot Sectors, Xip Enabled, Serial Flash Memory With 108 Mhz Spi Bus Interface
Manufacturer
Numonyx
Datasheet
1.N25Q128.pdf
(180 pages)
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9.2.3
Note:
9.2.4
DQ0
DQ1
C
S
0
Instruction
1
2
Read OTP (ROTP)
The Read OTP (ROTP) instruction is used to read the 64 bytes OTP area in the DIO-SPI
protocol. The instruction functionality is exactly the same as the Read OTP instruction of the
Extended SPI protocol; the only difference is that in the DIO-SPI protocol instruction code,
address and output data are all parallelized on the two pins DQ0 and DQ1.
The dummy bits can not be parallelized since these clock cycles are requested to perform
the internal reading operation.
Figure 44. Read OTP instruction and data-out sequence DIO-SPI
Write Enable (WREN)
The Write Enable (WREN) instruction sets the Write Enable Latch (WEL) bit.
Apart form the parallelizing of the instruction code on the two pins DQ0 and DQ1, the
instruction functionality is exactly the same as the Write Enable (WREN) instruction of the
Extended SPI protocol.
Figure 45. Write Enable instruction sequence DIO-SPI
3
S
C
DQ0
DQ1
23 21 19 17
22 20 18 16
4
5
6
7
24-Bit Address
15 13 11 9
14 12 10 8
8
9 10 11
0
Instruction
12 13 14 15
7
6
5
4
1
3
2
2
1
0
3
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33
Dual_Write_Enable
4
Dummy cycles
MSB
7
6
Data Out 1
5
4
3
2
1
0
Dual_Read_OTP
MSB
6
7
Data Out n
4
5
2
3
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