N25Q128 Numonyx, N25Q128 Datasheet - Page 138

• Manufacturer Part Number: N25Q128
• Description: 128-mbit 3 V, Multiple I/o, 4-kbyte Subsector Erase On Boot Sectors, Xip Enabled, Serial Flash Memory With 108 Mhz Spi Bus Interface
• Manufacturer: Numonyx

9.3.7
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DQ0
DQ3
DQ1
DQ2
C
S
Mode 3
Mode 0
Figure 77. Quad Command Page Program instruction sequence QIO-SPI, 32h
Program OTP instruction (POTP)
The Program OTP instruction (POTP) is used to program at most 64 bytes to the OTP
memory area (by changing bits from 1 to 0, only). Before it can be accepted, a Write Enable
(WREN) instruction must previously have been executed.
Apart form the parallelizing of the instruction code, address and input data on the four pins
DQ0, DQ1, DQ2 and DQ3, the instruction functionality (as well as the locking OTP method)
is exactly the same as the Program OTP (POTP) instruction of the Extended SPI protocol,
please refer to
0
1
20 16 12 8
21 17 13 9
22 18 14 10
23 19 15 11
2
Section 9.1.16: Program OTP instruction (POTP)
24-bit address
3
4
5
4
5
6
7
6
0
1
2
3
7
4
6
5
7
1
8
0
2
1
3
9 10 11 12 13 14
4
6
5
MSB
7
2
Data In
0
2
1
3
4
6
5
MSB
7
3
0
1
2
3
4
6
5
7
MSB
4
0
2
1
15
3
514
6
4
5
7
MSB
254
for further details.
Quad_Command_Page_Program_12h
Data In
515
0
1
2
3
516
4
5
6
7
MSB
255
517
0
2
1
3
518
4
5
6
7
256
MSB
519
0
1
2
3