S1D13700F01 Epson Electronics America, Inc., S1D13700F01 Datasheet - Page 36

• Manufacturer Part Number: S1D13700F01
• Description: Embedded Memory Graphics Lcd Controller
• Manufacturer: Epson Electronics America, Inc.

Page 36
7.3.6 Display Memory Access Timing for Text Mode
1. tOSC
2. DIV
3. Accesses to the display memory are allowed during this time period. It begins from the falling edge of FPLINE
S1D13700F01
X42A-A-002-04
FPSHIFT
FPLINE
and is defined by the following formulas depending on the selected color depth (1, 2, or 4 bpp).
For 1 bpp, use the following formula: ((TCR + 1) - (CR + 1) - 3) x DIV x 2 x tOSC
For 2 bpp, use the following formula: ((TCR + 1) - (CR + 1) - 2) x DIV x 2 x tOSC
For 4 bpp, use the following formula: ((TCR + 1) - (CR + 1) - 1) x DIV x 2 x tOSC
= 1/fOSC
= 1 cycle of the oscillator or the CLKI input clock
= OSC Divider (CNF[1:0])
= 4 or 8 or 16
When the microprocessor accesses the display memory, the following timing should be
followed. The falling edge of FPLINE can be used as the interrupt signal. Accessing the
display memory during times other than the recommended period may result in flickering
on the display.
Memory Access
Recommended
Note 3
Figure 7-9 Display Memory Access Timing
Not Recommended
Memory Access
Revision 4.05
Memory Access
Recommended
Note 3
Not Recommended
Memory Access
Epson Research and Development
Hardware Functional Specification
Vancouver Design Center
Issue Date: 2005/12/13