RS8973 Mindspeed Technologies, RS8973 Datasheet - Page 95

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RS8973

Manufacturer Part Number
RS8973
Description
Single-chip Sdsl/hdsl Transceiver
Manufacturer
Mindspeed Technologies
Datasheet

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RS8973
Single-Chip SDSL/HDSL Transceiver
Table 5-7. Channel Unit Interface Timing Requirements, Parallel Master Mode
Table 5-8. Channel Unit Interface Switching Characteristics, Parallel Master Mode
Figure 5-3. Channel Unit Interface Timing, Parallel Master Mode
N8973DSD
Symbol
Symbol
14
15
16
17
TQ[1,0] setup prior to QCLK falling edge
TQ[1,0] hold after QCLK low
RQ[1,0] hold after QCLK rising edge
RQ[1,0] delay after QCLK high
RQ[1,0]
TQ[1,0]
QCLK
5.5 Channel Unit Interface Timing
Tables 5-7
switching characteristics.
timing in parallel master mode, parallel slave mode, and serial mode, respectively.
16
Parameter
Parameter
through
17
Preliminary Information
5-12
Conexant
list channel unit interface timing requirements and
Figures 5-3
14
15
through
5.0 Electrical and Mechanical Specifications
5-5
illustrate channel unit interface
Minimum
Minimum
5.5 Channel Unit Interface Timing
100
–50
25
Maximum
Maximum
50
Units
Units
ns
ns
ns
ns
5-7

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