RS8973 Mindspeed Technologies, RS8973 Datasheet - Page 39

• Manufacturer Part Number: RS8973
• Description: Single-chip Sdsl/hdsl Transceiver
• Manufacturer: Mindspeed Technologies

RS8973
Single-Chip SDSL/HDSL Transceiver
2.3.1 Timing Recovery Circuit
2.3.2 Crystal Amplifier
2.3.3 Clock Synthesizer
N8973DSD
The timing recovery circuit uses the RS8973’s internal detected symbol and
equalizer error signals to regenerate the received data symbol clock (QCLK). The
HCLK output is synchronized with the edges of the symbol clock (QCLK), unlike
the XOUT output, which is a buffered output of the crystal amplifier. HCLK can
be programmed for rates of 16, 32, or 64 times the symbol rate.
average value of a phase correction signal. This information can be used during
start-up to set the phase offset in the Receive Phase Select Register
[receive_phase_select; 0x07]. The output of the phase detector is accumulated
over the meter timer interval [meter_low, meter_high; 0x18, 0x19]. At the end of
the measurement interval, the value is loaded into the Phase Detector Meter
Register [pdm_low, pdm_high; 0x40, 0x41].
frequency through the PLL Frequency Register [pll_frequency_low,
pll_frequency_high; 0x5E, 0x5F].
The crystal amplifier reduces the support circuitry needed for the RS8973 by
eliminating the need for an external crystal oscillator (XO). A crystal of
10.24 MHz frequency can be connected directly to the XTALI and XTALO pins.
The crystal amplifier can also accommodate an external clock input by
connecting the external clock to the XTALI input pin.
The clock synthesizer takes the 10.24 MHz input clock as a reference and
generates internal clocks required for data rates ranging from 144 kbps to
2320 kbps. The appropriate internal clock frequency can be selected by
specifying the data rate in the Clock Frequency Select Register [clk_select [7:0];
0x20] and PLL Modes Register [clk_select [9,8]; 0x22].
The timing recovery circuit includes a phase detector meter that measures the
The user can also bypass the timing recovery circuit and directly specify the
Preliminary Information
Conexant
2.3 Timing Recovery and Clock Interface
2.0 Functional Description
2-15