RS8973 Mindspeed Technologies, RS8973 Datasheet - Page 68

• Manufacturer Part Number: RS8973
• Description: Single-chip Sdsl/hdsl Transceiver
• Manufacturer: Mindspeed Technologies

3.0 Registers
3.3 Register Description
A 7-bit read/write register representing an unsigned binary number. The contents of this register are used to test
for scrambler synchronization during the automatic-scrambler synchronization mode of the symbol detector.
The test passes when the count of equivalent scrambler and detector output bits is greater than the value of this
register. When the auto-scrambler sync mode is not enabled, the contents of this register are not used.
far_end_high_alarm_th_high)
A 2-byte read/write register interpreted as a 16-bit, 2s-complement number. The range of meaningful values is
limited to positive integers between 0x0000 and 0x7FFF. The value of this register is compared to the value of
the far-end level meter. If the meter reading is greater than this threshold, the high_felm interrupt flag is set in
the IRQ Source Register [irq_source; 0x05].
far_end_low_alarm_th_high)
A 2-byte read/write register interpreted as a 16-bit, 2s-complement number. The range of meaningful values is
limited to positive integers between 0x0000 and 0x7FFF. The value of this register is compared to the value of
the far-end level meter. If the meter reading is less than this threshold, the low_felm interrupt flag is set in the
IRQ Source Register [irq_source; 0x05].
A 2-byte read/write register interpreted as a 16-bit, 2s-complement number. The range of meaningful values is
limited to positive integers between 0x0000 and 0x7FFF. The value of this register is compared to the value of
the SNR alarm meter. If the meter reading is greater than this threshold, the low_snr interrupt flag is set in the
IRQ Source Register [irq_source; 0x05].
A 2-byte read/write register interpreted as a 16-bit, 2s-complement number. The range of meaningful values is
limited to positive integers between 0x0000 and 0x2AAA (one-third of the maximum positive value). The value
of this register represents the expected level of a noise-free + 1 receive symbol at the slicer input. It is multiplied
by 2 to produce the positive and negative slicing levels, in addition to 0, used by the symbol detector in
four-level slicing mode. This value is also used to scale the detector output when computing the equalizer error
and slicer error signals. The detected symbol (– 3, – 1, + 1, + 3) is multiplied by the value of this register to
produce the scaled output.
A 2-byte read/write register interpreted as a 16-bit, 2s-complement number. The range of meaningful values is
limited to positive integers between 0x0000 and 0x7FFF. The value of this register is subtracted from the
absolute value of the receive signal at the output of the DAGC function. The difference is used as the error input
to the DAGC while in the self-adaptation mode. In the DAGC’s equalizer-error adaptation mode, the contents of
this register are not used.
3-22
0x2E—Scrambler Synchronization Threshold Register (scr_sync_th)
0x30, 0x31—Far-End High Alarm Threshold Register (far_end_high_alarm_th_low,
0x32, 0x33—Far-End Low Alarm Threshold Register (far_end_low_alarm_th_low,
0x34, 0x35—SNR Alarm Threshold Register (snr_alarm_th_low, snr_alarm_th_high)
0x36, 0x37—Cursor Level Register (cursor_level_low, cursor_level_high)
0x38, 0x39—DAGC Target Register (dagc_target_low, dagc_target_high)
—
7
D[6]
6
D[5]
5
Preliminary Information
D[4]
4
Conexant
D[3]
3
D[2]
Single-Chip SDSL/HDSL Transceiver
2
D[1]
1
N8973DSD
RS8973
D[0]
0