RS8973 Mindspeed Technologies, RS8973 Datasheet - Page 75

• Manufacturer Part Number: RS8973
• Description: Single-chip Sdsl/hdsl Transceiver
• Manufacturer: Mindspeed Technologies

RS8973
Single-Chip SDSL/HDSL Transceiver
A 2-byte read-only register containing 16 MSBs of the 32-bit unsigned noise-level meter accumulator. This
meter sums the absolute value of the detector’s slicer-error signal over each Meter Timer countdown interval.
Automatically loaded at the end of each interval, the meter register must be read the low byte first, followed by
high byte, unseparated by any other meter access (addresses 0x40 to 0x5F).
A 2-byte read/write register comprising 16 MSBs of the 31-bit, 2s-complement timing recovery loop
compensation filter accumulator. Treated much like a meter register, the frequency register must be read low
byte first, followed by high byte, unseparated by any other meter access (addresses 0x40 to 0x5F). Writes must
occur in the same order, with the low byte written first, followed by the high byte. Write accesses can be
separated by any number of other read or write accesses.
A 7-bit read/write register representing an unsigned binary address defined over a range of 0 to 119 decimal.
When written, it causes the selected 32-bit coefficient of the LEC to be subsequently loaded into the Access
Data Register [access_data_byte[3:0]; 0x7C–0x7F] within 2 symbol periods. Does not affect the value of the
coefficient. No other data access should occur between the time the Read Tap Select Register is written and the
time the Access Data Register is read, or the data may be corrupted.
A 7-bit read/write register representing an unsigned binary address defined over a range of 0 to 119 decimal.
When written, it causes all 32 bits of the Access Data Register [access_data_byte[3:0]; 0x7C–0x7F] to be
subsequently written to the selected LEC coefficient within 2 symbol periods. Does not affect the value of the
access data register.
N8973DSD
0x50, 0x51—Noise Level Meter Register (nlm_low, nlm_high)
0x5E, 0x5F— PLL Frequency Register (pll_frequency_low, pll_frequency_high)
0x70—LEC Read Tap Select Register (linear_ec_tap_select_read)
0x71—LEC Write Tap Select Register (linear_ec_tap_select_write)
D[23]
D[31]
D[22]
D[30]
—
—
7
7
7
7
D[22]
D[30]
D[21]
D[29]
D[6]
D[6]
6
6
6
6
D[21]
D[29]
D[20]
D[28]
D[5]
D[5]
5
5
5
5
Preliminary Information
D[20]
D[28]
D[19]
D[27]
D[4]
D[4]
4
4
4
4
Conexant
D[19]
D[27]
D[18]
D[26]
D[3]
D[3]
3
3
3
3
D[18]
D[26]
D[17]
D[25]
D[2]
D[2]
2
2
2
2
D[17]
D[25]
D[16]
D[24]
D[1]
D[1]
3.3 Register Description
1
1
1
1
3.0 Registers
D[16]
D[24]
D[15]
D[23]
D[0]
D[0]
0
0
0
0
3-29