RS8973 Mindspeed Technologies, RS8973 Datasheet - Page 57

• Manufacturer Part Number: RS8973
• Description: Single-chip Sdsl/hdsl Transceiver
• Manufacturer: Mindspeed Technologies

RS8973
Single-Chip SDSL/HDSL Transceiver
tbclk_pol
rbclk_pol
fifos_mode
interface_
mode[1,0]
N8973DSD
0x06—Channel Unit Interface Modes Register (cu_interface_modes)
Interface
Mode
[1:0]
—
00
01
10
11
7
Parallel master—Parallel quat transfer
synchronized to QCLK out.
Parallel slave—Parallel quat transfer
synchronized to separate TBCLK and
RBCLK inputs.
Serial, magnitude first—Serial quat
transfer synchronized to BCLK out;
magnitude-bit first, followed by sign
bit.
Serial, sign first—Serial quat transfer
synchronized to BCLK out; sign-bit
first, followed by magnitude bit.
Transmit Baud Clock Polarity—Read/write control bit defines the polarity of the TBCLK
input while in the parallel slave interface mode. When tbclk_pol is set, TQ[1,0] is sampled on
the falling edge of TBCLK; when cleared, TQ[1,0] is sampled on the rising edge.
Receive Baud Clock Polarity—Read/write control bit defines the polarity of the RBCLK input
while in the parallel slave interface mode. When rbclk_pol is set, RQ[1,0] is updated on the
falling edge of RBCLK; when cleared, RQ[1,0] is updated on the rising edge.
FIFO’s Mode—Read/write control bit used to stagger the transmit and receive the FIFO’s read
and write pointers while in the parallel slave interface mode. A logical 1 forces the pointers to
a staggered position; a logical 0 allows them to operate normally. To maximize phase-error
tolerance, fifos_mode must be first set, then cleared once after QCLK-TBCLK-RBCLK
frequency lock is achieved.
Interface Mode—Read/write binary field specifies one of four operating modes for the
channel unit interface.
—
6
Mode
—
5
tbclk_pol
Preliminary Information
4
Conexant
TBCLK
used
used
used
Not
Not
Not
91
rbclk_pol
3
RBCLK
used
used
used
Not
Not
Not
90
fifos_mode
RQ[1]
RQ[1]
RDAT
RDAT
2
Pin Functions
88
interface_mode[1] interface_mode[0]
RQ[0]
RQ[0]
BCLK
BCLK
89
1
3.3 Register Description
TQ[1]
TQ[1]
TDAT
TDAT
85
3.0 Registers
0
TQ[0]
TQ[0]
used
used
Not
Not
86
3-11