RS8973 Mindspeed Technologies, RS8973 Datasheet - Page 21

• Manufacturer Part Number: RS8973
• Description: Single-chip Sdsl/hdsl Transceiver
• Manufacturer: Mindspeed Technologies

RS8973
Single-Chip SDSL/HDSL Transceiver
Table 1-2. Hardware Signal Definitions (3 of 4)
N8973DSD
TBCLK
RBCLK
TXP, TXN
RXP, RXN
RXBP, RXBN
RBIAS
VCOMO
VCOMI
VCCAP
VRXP, VRXN
VTXP, VTXN
XTALI/
MCLK
XTALO
HCLK
XOUT
Pin Label
Transmit
Baud-Rate Clock
Receive Baud-Rate
Clock
Transmit Positive,
Negative
Receive Positive,
Negative
Receive Balance
Positive, Negative
Resistor Bias
Common Mode
Voltage Outputs
Common Mode
Voltage Inputs
Voltage
Compensation
Capacitor
Receiver Voltage
Reference
Positive, Negative
Transmit Voltage
Reference
Positive, Negative
Crystal In/Master
Clock
Crystal Output
High Speed Clock
Out
Crystal Clock Out
Signal Name
I/O
OA
OA
OA
OA
OA
OA
OA
IA
IA
O
O
O
I
I
I
Voltage Reference Generator Interface
Functions as the transmit baud-rate clock input. It must be frequency-locked to
QCLK. This input is used only when the channel unit interface is in parallel slave
mode. If it is unused, it should be tied to VDD2 or DGND.
Functions as the receive baud-rate clock input. It must be frequency-locked to
QCLK. This input is used only when the channel unit interface is in parallel slave
mode. If it is unused, it should be tied to VDD2 or DGND.
Differential transmit line driver outputs. These signals are used to drive the
subscriber line after passing through the hybrid and line transformer.
Differential receiver inputs. RXP and RXN receive the signal from the subscriber
line.
Differential receiver balance inputs. RXBP and RXBN are used to subtract the
echo of the signal being transmitted on the subscriber line. They should be
connected to the TXP, TXN output pins through the hybrid circuit. This signal is
subtracted from the signal being received by the RXP and RXN inputs in the
VGA.
Connection point for external bias resistor.
Common mode voltage for the analog circuitry. This pin should be connected to
an external filtering capacitor.
Common mode voltage for the analog circuitry. This pin should be connected to
an external filtering capacitor.
Analog voltage compensation capacitor. This pin should be connected to an
external filtering capacitor.
Analog receive circuitry reference voltages. These pins should be connected to
external filtering capacitors.
Analog transmit circuitry reference voltages. These pins should be connected to
external filtering capacitors.
A bimodal input that can be used as the crystal input or as the master clock
input. The frequency of the crystal or clock should be 10.24 MHz.
Connection point for the crystal. If an external clock is connected to
XTALI/MCLK, XTALO should be left floating.
HCLK can be configured to run at 16, 32, or 64 times the symbol rate. Upon
reset, it is set to 16 times the symbol rate. This clock will be phase locked to the
incoming data when the RS8973 is configured as the remote unit.
Buffered-crystal oscillator output.
Analog Transmit Interface
Preliminary Information
Analog Receive Interface
Clock Interface
Conexant
Definition
1.0 System Overview
1.2 Pin Descriptions
1-9