RS8973 Mindspeed Technologies, RS8973 Datasheet - Page 72

• Manufacturer Part Number: RS8973
• Description: Single-chip Sdsl/hdsl Transceiver
• Manufacturer: Mindspeed Technologies

3.0 Registers
3.3 Register Description
zero_output
zero_coefficients
adapt_coefficents
adapt_gain
A 2-byte read-only register containing the 16 MSBs of the 26-bit, 2s-complement phase detector meter
accumulator. This meter sums the output of the timing recovery module’s phase detector over each Meter Timer
countdown interval, before being offset by the Phase Offset Register [pll_phase_offset_low,
pll_phase_offset_high; 0x24, 0x25]. Automatically loaded at the end of each interval, the meter register must be
read low byte first, followed by high byte, unseparated by any other meter access (addresses 0x40 to 0x5F).
A single-byte read-only register containing all 8 bits of the unsigned overflow meter accumulator. This meter
counts the number of ADC overflow conditions which occur during each meter timer countdown interval,
limited to a maximum count of 255 (0xFF). The meter register is automatically loaded at the end of each
countdown interval.
3-26
0x3E—Error Predictor Modes Register (ep_modes)
0x40, 0x41—Phase Detector Meter Register (pdm_low, pdm_high)
0x42—Overflow Meter Register (overflow_meter)
D[17]
D[25]
D[7]
—
7
7
7
Zero Output—Read/write control bit that, when set, zeros the error predictor correction signal
before subtraction at the slicer. Achieves the affect of disabling, or bypassing, the error
predictor function. Does not disable coefficient adaptation. When cleared, normal error
predictor operation is performed.
Zero Coefficients—Read/write control bit that, with coefficient adaptation enabled
(adapt_coefficients = 1), continuously zeros all coefficients when set; allows normal
coefficient updates when cleared. If coefficient adaptation is disabled (adapt_coefficients = 0),
this control bit has no affect. This behavior differs slightly from the similar function
(zero_coefficients) of the LEC, NEC, and DFE filters. Whenever this bit is set, it must be
accompanied by adapt_coefficients (set) for a 2-symbol time period.
Adapt Coefficients—Read/write control bit that enables coefficient adaptation when set and
disables/freezes adaptation when cleared. Coefficient values are preserved when adaptation is
disabled.
Adaptation Gain—Read/write control bit that specifies the adaptation gain. When this bit is
set, the adaptation gain is four times higher than when cleared.
D[16]
D[24]
D[6]
—
6
6
6
D[15]
D[23]
D[5]
—
5
5
5
Preliminary Information
D[14]
D[22]
D[4]
—
4
4
4
Conexant
zero_output
D[13]
D[21]
D[3]
3
3
3
zero_coefficients
D[12]
D[20]
D[2]
Single-Chip SDSL/HDSL Transceiver
2
2
2
coefficients
adapt_
D[11]
D[19]
D[1]
1
1
1
N8973DSD
adapt_gain
RS8973
D[10]
D[18]
D[0]
0
0
0