RS8973 Mindspeed Technologies, RS8973 Datasheet - Page 19

• Manufacturer Part Number: RS8973
• Description: Single-chip Sdsl/hdsl Transceiver
• Manufacturer: Mindspeed Technologies

RS8973
Single-Chip SDSL/HDSL Transceiver
Table 1-2. Hardware Signal Definitions (1 of 4)
N8973DSD
MOTEL
ALE
CS
RD/DS
WR / R/W
AD[7:0]
ADDR[7:0]
MUXED
READY
IRQ
Pin Label
Motorola/Intel
Address Latch
Enable
Chip Select
Read/Data Strobe
Write/
Read/Write
Address-Data[7:0]
Address Bus (not
multiplexed)[7:0]
Addressing Mode
Select
Ready
Interrupt Request
Signal Name
column:
Signal definitions are provided in
O
OA = analog output
OD = open-drain output
I
IA = analog input
I/O = bidirectional
NC = no connect
I/O
I/O
OD
OD
I
I
I
I
I
I
I
= digital output
= digital input
Microcomputer Interface (MCI)
Selects between Motorola and Intel handshake conventions for the RD/DS and
WR/R/W signals.
Falling-edge-sensitive input. The value of AD[7:0] when MUXED = 1, or
ADDR[7:0] when MUXED = 0, is internally latched on the falling edge of ALE.
Active-low input used to enable read/write operations on the MCI.
Bimodal input for controlling read/write access on the MCI.
DS. Internal data is output on AD[7:0] when DS = 0 and R/W = 1. External data
is internally latched from AD[7:0] on the rising edge of DS when R/W = 0.
RD. Internal data is output on AD[7:0] when RD = 0. Write operations are not
controlled by RD in this mode.
Bimodal input for controlling read/write access on the MCI.
R/W. Internal data is output on AD[7:0] when DS = 0 and R/W = 1. External data
is internally latched from AD[7:0] on the rising edge of DS when R/W = 0.
WR. External data is internally latched from AD[7:0] on the rising edge of WR.
Read operations are not controlled by WR in this mode.
An 8-bit, bidirectional multiplexed address-data bus. AD[7] = MSB, AD[0] =
LSB. Usage is controlled using MUXED.
Provides a glueless interface to microcomputers with separate address and data
buses. ADDR[7] = MSB, ADDR[0] = LSB. Usage is controlled using MUXED.
Controls the MCI addressing mode.
and data.
AD[7:0] for data only.
Active-low, open-drain output that indicates the MCI is ready to transfer data.
Can be used to signal the microcomputer to insert wait states.
Active-low, open-drain output that indicates requests for interrupt. Asserted
whenever at least one unmasked interrupt flag is set. Remains inactive
whenever no unmasked interrupt flags are present.
Preliminary Information
MOTEL = 1 for Motorola protocol: DS, R/W
MOTEL = 0 for Intel protocol: RD, WR
When MOTEL = 1 and CS = 0, RD/DS behaves as an active-low data strobe
When MOTEL = 0 and CS = 0, RD/DS behaves as an active-low read strobe
When MOTEL = 1 and CS = 0, WR/R/W behaves as a read/write select line
When MOTEL = 0 and CS = 0, WR/R/W behaves as an active-low write strobe
When MUXED = 1, the MCI uses AD[7:0] as a multiplexed signal for address
When MUXED = 0, the MCI uses ADDR[7:0] as the address input, and
Conexant
Table
Definition
1-2. This is the coding used in the I/O
1.0 System Overview
1.2 Pin Descriptions
1-7