A43P26161 AMIC Technology, Corp., A43P26161 Datasheet - Page 33

• Manufacturer Part Number: A43P26161
• Description: 1M x 16-Bit x 4 Banks Low Power Synchronous DRAM
• Manufacturer: AMIC Technology, Corp.

Write Interrupted by Precharge Command & Write Burst Stop Cycle @ Burst Length = Full Page
PRELIMINARY
CLOCK
A10/AP
ADDR
DQM
CKE
RAS
CAS
BS1
BS0
CS
WE
DQ
* Note : 1. At full page mode, burst is wrap-around at the end of burst. So auto precharge is impossible.
0
Row Active
(A-Bank)
RAa
RAa
1
2. Data-in at the cycle of interrupted by precharge cannot be written into the corresponding memory cell.
3. Burst stop is valid at every burst length.
(July, 2005, Version 1.1)
It is defined by AC parameter of t
DQM at write interrupted by precharge command is needed to prevent invalid write.
DQM should mask invalid input data on precharge command cycle when asserting precharge before end of burst.
Input data after Row precharge cycle will be masked internally.
2
3
(A-Bank)
Write
DAa0
CAa
4
DAa1
5
DAa2
6
DAa3
RDL
7
(=2CLK).
DAa4
8
t
Burst Stop
BDL
9
32
High
10
(A-Bank)
DAb0
Write
CAb
11
DAb1
12
DAb2
13
DAb3
14
AMIC Technology, Corp.
DAb4
15
DAb5
* Note 2
16
t
RDL
17
Precharge
(A-Bank)
A43P26161
18
: Don't care
19