A43P26161 AMIC Technology, Corp., A43P26161 Datasheet - Page 2

• Manufacturer Part Number: A43P26161
• Description: 1M x 16-Bit x 4 Banks Low Power Synchronous DRAM
• Manufacturer: AMIC Technology, Corp.

Preliminary
Features
General Description
The
synchronous high data rate Dynamic RAM organized as 4
X 1,048,576 words by 16 bits, fabricated with AMIC’s high
performance CMOS technology. Synchronous design
allows precise cycle control with the use of system clock.
Pin Configuration
PRELIMINARY
54 Balls CSP (8 mm x 8 mm)
Top View
Low power supply
- VDD: 2.5V
Four banks / Pulse RAS
MRS cycle with address key programs
- CAS Latency (2 & 3)
- Burst Length (1,2,4,8 & full page)
- Burst Type (Sequential & Interleave)
All inputs are sampled at the positive going edge of the
system clock
Deep Power Down Mode
DQM for masking
Auto & self refresh
Clock Frequency (max) : 105MHz @ CL=3 (-95)
LVCMOS compatible with multiplexed address
A43P26161
VDDQ : 2.5V
(July, 2005, Version 1.1)
is
C
D
G
H
A
B
E
F
J
67,108,864
133MHz @ CL=3 (-75)
UDQM
DQ
DQ
DQ
VSS
VSS
DQ
NC
A8
1M X 16 Bit X 4 Banks Low Power Synchronous DRAM
1
14
12
10
8
bits
DQ
DQ
DQ
DQ
CLK
A11
NC
A7
A5
2
Low
15
13
11
54 Ball (6X9) CSP
9
Power
VDDQ
VDDQ
VSSQ
VSSQ
VSS
CKE
A9
A6
A4
3
1
VDDQ
VSSQ
VDDQ
VSSQ
CAS
VDD
BA0
I/O transactions are possible on every clock cycle. Range
of operating frequencies, programmable latencies allows
the same device to be useful for a variety of high
bandwidth,
applications.
A0
A3
7
Self refresh with programmable refresh period through
EMRS cycle
Programmable Power Reduction Feature by partial
array activation during Self-refresh through EMRS
cycle
Industrial operating temperature range: -40ºC to +85ºC
for -U series.
Available in 54 Balls CSP (8mm X 8mm) and 54-pin
TSOP(II) packages.
Package is available to lead free (-F series)
64ms refresh period (4K cycle)
LDQM
RAS
DQ
DQ
DQ
DQ
BA1
A1
A2
8
high
0
2
4
6
VDD
VDD
DQ
DQ
DQ
DQ
performance
WE
A10
CS
AMIC Technology, Corp.
9
1
3
5
7
A43P26161
memory
system