A43P26161 AMIC Technology, Corp., A43P26161 Datasheet - Page 10

• Manufacturer Part Number: A43P26161
• Description: 1M x 16-Bit x 4 Banks Low Power Synchronous DRAM
• Manufacturer: AMIC Technology, Corp.

Mode Register Filed Table to Program Modes
Register Programmed with MRS
Note : 1. RFU(Reserved for Future Use) should stay “0” during MRS cycle.
Extended Mode Register Table
Note: BS1 and BS0 must be 1, 0 to select the Extended Mode Register (vs. the Mode Register)
PRELIMINARY
A9
A8
BS1
A6
0
1
Address
0
0
1
1
Function
0
0
1
↓
1
(Note)
2. If A9 is high during MRS cycle, “Burst Read Single Bit Write” function will be enabled.
A7
3. BS0, BS1 must be 0,0 to select the Mode Register (vs. the Extended Mode Register).
Write Burst Length
A5
0
1
0
1
Driver Strength
0
1
0
BS0
↓
0
Test Mode
Driver Strength
Mode Register Set
BS1
Single Bit
0
Length
A11, A10
Burst
(Note 3)
(July, 2005, Version 1.1)
Full
1/2
1/4
Vendor
Type
↓
Only
Use
Driver Strength
All have to be set to “0”
BS0
0
Temperature-Compensated Self-Refresh:
A9
↓
A11,A10
(Note 1)
RFU
A4
0
A6
0
1
1
0
0
0
0
1
1
1
1
A8
↓
A5
0
0
1
1
0
0
1
1
A3
CAS Latency
0
1
0
1
(Note 2)
W.B.L
A7
↓
A9
A4
0
1
0
1
0
1
0
1
Max. Case Temp.
A6
Reserved
Reserved
Reserved
Reserved
Reserved
↓
Latency
70 ° C
45 ° C
15 ° C
85 ° C
A8
DS
2
3
-
TM
A5
↓
9
A7
A3
0
1
Burst Type
A4
↓
A6
TCSR
Sequential
Interleave
CAS Latency
A2
Type
0
0
0
0
1
1
1
1
A3
↓
A5
A1
A2
0
0
1
1
0
0
1
1
↓
A2
Partial-Array Self Refresh:
0
0
0
0
1
1
1
1
A4
AMIC Technology, Corp.
PASR
A1
A0
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
A1
↓
A3
BT
A0
0
1
0
1
0
1
0
1
Banks to be Self-Refreshed
Burst Length
A0
↓
Reserved
Reserved
Reserved
256(Full)
BT=0
Bank A, Bank B
A2
1/2 of Bank A
1/4 of Bank A
1
2
4
8
A43P26161
Address Bus (Ax)
Reserved
Reserved
Reserved
Burst Length
All banks
Bank A
A1
Reserved
Reserved
Reserved
Reserved
BT=1
1
2
4
8
A0