LPC2926_27_29 NXP Semiconductors, LPC2926_27_29 Datasheet - Page 49

• Manufacturer Part Number: LPC2926_27_29
• Description: The LPC2926/2927/2929 combine an ARM968E-S CPU core with two integrated TCMblocks operating at frequencies of up to 125 MHz, Full-speed USB 2
• Manufacturer: NXP Semiconductors

NXP Semiconductors
LPC2926_27_29
Product data sheet
Fig 11. PCRSS block diagram
AHB2DTL
BRIDGE
6.16.1 Clock description
reset from watchdog counter
OSCILLATOR
LOW POWER
OSCILLATOR
REGISTERS
REGISTERS
EXTERNAL
RST (device pin)
The PCRSS is clocked by a number of different clocks. CLK_SYS_PCRSS clocks the
AHB side of the AHB to DTL bus bridge and CLK_PCR_SLOW clocks the CGU, RGU and
PMU internal logic, see
BASE_SYS_CLK, which can be switched off in low-power modes. CLK_PCR_SLOW is
derived from BASE_PCR_CLK and is always on in order to be able to wake up from
low-power modes.
RING
CGU0
RGU
POR
FDIV[6:0]
PLL
All information provided in this document is subject to legal disclaimers.
RESET OUTPUT
DELAY LOGIC
DEGLITCH/
INPUT
SYNC
Rev. 5 — 28 September 2010
Section
OUT11
OUT6
OUT0
OUT1
OUT5
OUT7
OUT9
CGU0
RGU
6.7.2. CLK_SYS_PCRSS is derived from
ARM9 microcontroller with CAN, LIN, and USB
FDIV
PLL
OUT0
OUT1
OUT2
LPC2926/2927/2929
CGU1
PCR_RST
WARM_RST
RGU_RST
POR_RST
COLD_RST
AHB_RST
SCU_RST
REGISTERS
CONTROL
ENABLE
CLOCK
CLOCK
GATES
PMU
© NXP B.V. 2010. All rights reserved.
PMU
002aae244
wakeup_a
disable:
grant
request
master
branch
clocks
AHB
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