LPC2926_27_29 NXP Semiconductors, LPC2926_27_29 Datasheet - Page 29

• Manufacturer Part Number: LPC2926_27_29
• Description: The LPC2926/2927/2929 combine an ARM968E-S CPU core with two integrated TCMblocks operating at frequencies of up to 125 MHz, Full-speed USB 2
• Manufacturer: NXP Semiconductors

NXP Semiconductors
LPC2926_27_29
Product data sheet
6.12.1 General subsystem clock description
6.12.2 Chip and feature identification
6.12.3 System Control Unit (SCU)
6.12.4 Event router
6.12 General subsystem
The general subsystem is clocked by CLK_SYS_GESS, see
The Chip/Feature ID (CFID) module contains registers which show and control the
functionality of the chip. It contains an ID to identify the silicon and also registers
containing information about the features enabled or disabled on the chip.
The key features are:
The CFID has no external pins.
The system control unit contains system-related functions. The key feature is
configuration of the I/O port-pins multiplexer. It defines the function of each I/O pin of the
LPC2926/2927/2929. The I/O pin configuration should be consistent with peripheral
function usage.
The SCU has no external pins.
The event router provides bus-controlled routing of input events to the vectored interrupt
controller for use as interrupt or wake-up signals.
Key features:
The event router allows the event source to be defined, its polarity and activation type to
be selected and the interrupt to be masked or enabled. The event router can be used to
start a clock on an external event.
The vectored interrupt-controller inputs are active HIGH.
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Identification of product
Identification of features enabled
Up to 20 level-sensitive external interrupt pins, including the receive pins of SPI, CAN,
LIN, USB, and UART, as well as the I
sources.
Input events can be used as interrupt source either directly or latched
(edge-detected).
Direct events disappear when the event becomes inactive.
Latched events remain active until they are explicitly cleared.
Programmable input level and edge polarity.
Event detection maskable.
Event detection is fully asynchronous, so no clock is required.
All information provided in this document is subject to legal disclaimers.
Rev. 5 — 28 September 2010
ARM9 microcontroller with CAN, LIN, and USB
2
C-bus SCL pins plus three internal event
LPC2926/2927/2929
Section
6.7.2.
© NXP B.V. 2010. All rights reserved.
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