LPC2926_27_29 NXP Semiconductors, LPC2926_27_29 Datasheet - Page 40

The LPC2926/2927/2929 combine an ARM968E-S CPU core with two integrated TCMblocks operating at frequencies of up to 125 MHz, Full-speed USB 2

LPC2926_27_29

Manufacturer Part Number
LPC2926_27_29
Description
The LPC2926/2927/2929 combine an ARM968E-S CPU core with two integrated TCMblocks operating at frequencies of up to 125 MHz, Full-speed USB 2
Manufacturer
NXP Semiconductors
Datasheet
NXP Semiconductors
LPC2926_27_29
Product data sheet
Fig 8.
PAUSE
Modulation and Sampling Control SubSystem (MSCSS) block diagram
MSCSS
TIMER0
TIMER1
MSCSS
MSCSS
QEI
All information provided in this document is subject to legal disclaimers.
PWM0 TRAP
PWM0 CAP[2:0]
carrier
carrier
carrier
carrier
start
start
AHB-TO-APB BRIDGE
start
Rev. 5 — 28 September 2010
start
PWM1 TRAP
PWM1 CAP[2:0]
ADC0
PWM0
ADC1
PWM2 TRAP
synch
PWM2 CAP[2:0]
PWM1
synch
ADC2
synch
PWM3 TRAP
PWM3 CAP[2:0]
ARM9 microcontroller with CAN, LIN, and USB
synch
PWM2
synch
PWM3
LPC2926/2927/2929
IDX0
PHA0
PHB0
ADC0 IN[7:0]
ADC1 IN[7:0]
ADC2 IN[7:0]
ADC2 EXT START
PWM0 MAT[5:0]
PWM1 MAT[5:0]
PWM2 MAT[5:0]
PWM3 MAT[5:0]
© NXP B.V. 2010. All rights reserved.
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